04-08-2010 05:20 AM
If I just instantiate the XPS IIC core in my design and don't connect it to any other IIC compatible device (just to a Chipscope ILA core), like this:
PARAMETER INSTANCE = xps_iic_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81600000
PARAMETER C_HIGHADDR = 0x8160ffff
BUS_INTERFACE SPLB = plb0
PORT Scl = xps_iic_0_Scl
PORT Sda = xps_iic_0_Sda
PORT Scl_O = xps_iic_0_Scl_O_to_chipscope_ila_0
PORT Sda_O = xps_iic_0_Sda_O_to_chipscope_ila_0
And in my code I keep doing XIic_MasterSend in an infinite loop (Just trying to see whether I observe the xps_iic_0_Scl master clock signal in Chipscope, so I can proceed) , should I be able to view the master clock (16,384 samples, 100MHz clock, I keep re-buffering the scope)? Note please that I haven't connected any other IIC device. What I observe is constant 0 on xps_iic_0_Scl and xps_iic_0_Sda signals. I have seen the I2C bus electrical description (The open Collector/Drain stuff) but I am still unable to decide where the problem lies. Processor runs at 100MHz also. Please help. Thank you for reading.
04-08-2010 05:33 AM
SCL_o and SDA_o are not the right signals to be probed. They will always be "0" as you observed. And that's because it's open drain. Instead, you should probe _T, which is used to switch on/off the tri-state output buffer.
When _T is high, the output buffer will be closed and the line will be pulled high by the external pullup resistor. When _T is low, the output buffer will be open and then the value of _O will be placed on the line.
04-11-2010 11:57 PM
04-13-2010 12:40 AM