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3,597 Views
Registered: ‎07-06-2008

Debugging IIC signals with Chipscope

If I just instantiate the XPS IIC core in my design and don't connect it to any other IIC compatible device (just to a Chipscope ILA core), like this:

 

BEGIN xps_iic

 PARAMETER INSTANCE = xps_iic_0

 PARAMETER HW_VER = 2.00.a

 PARAMETER C_BASEADDR = 0x81600000

 PARAMETER C_HIGHADDR = 0x8160ffff

 BUS_INTERFACE SPLB = plb0

 PORT Scl = xps_iic_0_Scl

 PORT Sda = xps_iic_0_Sda

 PORT Scl_O = xps_iic_0_Scl_O_to_chipscope_ila_0

 PORT Sda_O = xps_iic_0_Sda_O_to_chipscope_ila_0

END

 

And in my code I keep doing XIic_MasterSend in an infinite loop (Just trying to see whether I observe the xps_iic_0_Scl master clock signal in Chipscope, so I can proceed) , should I be able to view the master clock (16,384 samples, 100MHz clock, I keep re-buffering the scope)? Note please that I haven't connected any other IIC device. What I observe is constant 0 on xps_iic_0_Scl and xps_iic_0_Sda signals. I have seen the I2C bus electrical description (The open Collector/Drain stuff) but I am still unable to decide where the problem lies. Processor runs at 100MHz also. Please help. Thank you for reading.

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3 Replies
Xilinx Employee
Xilinx Employee
3,595 Views
Registered: ‎08-07-2007

Re: Debugging IIC signals with Chipscope

SCL_o and SDA_o are not the right signals to be probed. They will always be "0" as you observed. And that's because it's open drain. Instead, you should probe _T, which is used to switch on/off the tri-state output buffer.

 

When _T is high, the output buffer will be closed and the line will be pulled high by the external pullup resistor. When _T is low, the output buffer will be open and then the value of _O will be placed on the line.

 

-Felix

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Visitor sachinm1984
Visitor
3,558 Views
Registered: ‎03-24-2010

Re: Debugging IIC signals with Chipscope

I was having a similar problem. I was using ILA using Core Inserter and connecting I2C_SCK_I and I2C_SDA_I signals to it. ChipScope showed them always to be ground.
Now I have added ILA in EDK itself and have connected _T signals to it. I am getting toggling on the SCK, but the data on SDA is not what I am expecting.
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3,545 Views
Registered: ‎07-06-2008

Re: Debugging IIC signals with Chipscope

I did probe the _T signals. They are both high, even though I keep sending some garbage data on the bus for verification in my C code in a loop. Wonder whats the reason?
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