11-18-2011 07:26 PM
I am trying to create a XPS project to test the axi_pcie core. I'm using ML605.
I am not quite clear about the details and cannot find any examples:(
What I want to know is:
- How to connect clock signals? Shall I connect AXI_ACLK_OUT to AXI_ACLK directly?
- It is said in the datasheet that "the MMCS_LOCK output must be connected to the DCM_Locked input of the Proc_Sys_Reset module", but DCM_Locked is already to an output of clock_generator.
- Should I insert pcie pin assignments into system.ucf?
...
Oh I really don't know how to make it work.
Dose anyone has a demo project? Then I can take it as a reference.
Thanks:)
11-18-2011 08:13 PM
http://www.xilinx.com/support/answers/43371.htm
@jerrylipeng wrote:
I am trying to create a XPS project to test the axi_pcie core. I'm using ML605.
I am not quite clear about the details and cannot find any examples:(
What I want to know is:
- How to connect clock signals? Shall I connect AXI_ACLK_OUT to AXI_ACLK directly?
- It is said in the datasheet that "the MMCS_LOCK output must be connected to the DCM_Locked input of the Proc_Sys_Reset module", but DCM_Locked is already to an output of clock_generator.
- Should I insert pcie pin assignments into system.ucf?
...
Oh I really don't know how to make it work.
Dose anyone has a demo project? Then I can take it as a reference.
Thanks:)
11-24-2011 12:42 AM