cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
6,489 Views
Registered: ‎02-13-2008

Double fifo size of uart lite

Hi,

I'm relatively new to using XPS, and have been tinkering around with some serial communication with the uart lite on a spartan 3an development board.  I am curious if it is possible to modify the fifo size of the send and recieve buffers though.  A 32 byte buffer would be much more suited for my purposes in the long run.  Does anyone know if this is feasible?

Thankyou,
wgibb
0 Kudos
2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
6,475 Views
Registered: ‎08-13-2007

Re: Double fifo size of uart lite

It is not possible as far as changing a simple parameter in the IP configuration to increase the FIFO size.
The FIFO size in this core is fixed at 16 bytes.
 
However, this core is available in plaintext in the EDK cores directory (e.g. %XILINX_EDK%\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_00_a\hdl\vhdl)
 
It is theoretically possible to copy this core to your local pcores, change the names, and modify the implementation to use a larger FIFO.
This is likely beyond the scope of what most people would want to do or support. But it is possible.
 
The size 16 deep comes from the SRL16. You would have to change the default FIFO implementation (e.g. cascade multiple SRL16 FIFOs or switch to a BRAM FIFO).
 
Cheers,
bt


Message Edited by timpe on 03-07-2008 03:29 AM
Highlighted
Visitor
Visitor
2,493 Views
Registered: ‎02-10-2014

Re: Double fifo size of uart lite

Hello, 

 

Is it possible if I just change the C_DEPTH within the within uartlite_tx/rx.vhdl file shouldn't it work I notice the fifo is setup as generic. 

 

I'mt using proc_common_v3_00_a.srl_fifo_f for the fido and the uartlite is version 1.02a

0 Kudos