05-24-2015 04:09 PM
I am running on a Virtex 7 (vc707 eval board) and originally the design had the board's LEDs driven from an AXI GPIO IP instantiated and connected to a Microblaze AXI Bus. I decided to change how one of the LEDs work, and instead of being driven from the Microblaze/GPIO IP, it would be driven automatically from HDL.
When I did this, I got:
"[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard...Problem ports: led_8bits_tri_o[0]"
So I am curious to how I was able to build the project before. Does the AXI GPIO IP automatically create I/O Standard contstraints? If so, what is the IO standard it is using?
05-25-2015 10:08 AM
05-26-2015 10:27 PM
Hi,
Check Table 1-26 on page 54 of http://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf to get LEDs pin location and IO standard.
Regards
Praveen
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