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Visitor cotret_pas
Visitor
7,996 Views
Registered: ‎01-25-2016

Driver for an AXI4-Stream based custom IP

(I'm working on 14.7 EDK tools)

Hi all,

the attached picture is a quick schematic of what I'm trying to do. In a few words :

- I have a MicroBlaze running my code.

- And an AXIStream-based IP (for test purposes, I used a simple adder). This IP was created using the CIP Wizard in XPS and it has 2 input 32-bit words and 1 output 32-bit word.

 

In order to link these two components, I added an "AXI FIFO Memory-mapped to streaming IP" as it is shown in my drawing.

 

I naively thought that the C code given with my CIP-based adder would handle the AXI FIFO settings but this is not the case...

I was looking for a driver/example of the FIFO initialization (C code to be put in my MicroBlaze) but I couldn't find it.

Is there any link/tutorial about how to write C code to drive the AXI FIFO IP (instead of reading the whole datasheet :p)

Sans titre.jpg
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1 Reply
Xilinx Employee
Xilinx Employee
7,943 Views
Registered: ‎08-06-2007

Re: Driver for an AXI4-Stream based custom IP

Hi,

 

Do you know that MicroBlaze has AXI-Stream interface directly to the core?

 

Read the MicroBlaze Fast Simplex Link (FSL) Interface Macros section in Standalone part(UG647) of the OS and Libraries Documentation Collection EDK 14.7 (UG643)

For Vivado designs these FSL Interfaces are in fact AXI-Streams, for EDK designs these interfaces can either be FSL or AXI-Streams.

 

For more information about MicroBlaze FSL(AXI-Stream) interface read the MicroBlaze Reference Guide EDK 14.7

 

Göran

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