11-18-2019 11:47 PM - edited 11-19-2019 04:16 PM
I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "Xmyip_LookupConfig", "Xmyip_CfgInitialize" etc with which I was able to initialize my IP 'myip' and use the function "XAxiDma_SimpleTransfer" to send AXI-stream input data to/from PL/PS.
But if I create any custom-IP (not HLS, but using Create and Package New-IP under tools), in the same name ('myip'), headerfile myip.h (not xmyip.h like in case of HLS) got generated. And also it has the following functions only
#define MYIP2_mReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
#define MYIP2_mWriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
There are no util/wrapper functions ("Xmyip_LookupConfig", "Xmyip_CfgInitialize") like in the case of HLS IP to initialize my IP core. How do I proceed in this case?
11-21-2019 12:05 PM
I'm not really familiar with HLS but as you already notice the default Vivado Custom IP wizard just provides a very basic driver code (as you already said just a C file and Header file). That means that you would need to write your own drivers, either completelly custom or based on our default drivers.
The HLS cores have DMA engines on it by default and that's why the tool provides a generic driver to handle transactions and initialize the code. In Vivado IP the IPs are much more divers and can go from simple register to really complex design, so there is no way to provide a generic driver code that suits all of them.
11-21-2019 04:41 PM
Hello @ibaie ,
Thank You for your reply. As the registers used for AXI stream are memory-mapped, I can find the related addresses and read/write to these using the generated functions from the header file for transferring the data. But what should I do to initialize the IP? Or how am I supposed to use the generated functions in the header file to initialize the IP? Can you please direct me to an example.
11-25-2019 02:15 PM
You AXI ports in the IP probably are either AXI4 or AXI-Lite (no AXI Stream), which are memory-mapped interfaces. The address of the IP can be found either in your Vivado design within the Address Editor or the xparameters.h file in your BSP which is auto-generated based on the Vivado design.
The IP does not have any initialization requirement, is up to your design. What I mean is that the memory mapped register are available from the beggining so you can do read/write operations. Then if you design your IP in a way that you need to write some register to start whaterver function you want to perform, then is completelly up to your design.
11-26-2019 10:28 AM
11-26-2019 08:59 PM
11-27-2019 12:19 AM
the xparameters.h file is populated by the TCL file in the data folder of your IP.
Take the gpio for example:
For example, the ::hsi::utils::define_include_file.
do yu have something similar on your end?
Can you share your driver?