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vras
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Registered: ‎12-22-2020

Drivers and Makefiles problems in Vitis 2020.2

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Hello everyone!

I have created a custom AXI4-Lite IP in Vivado 2020.2 and when I use Vitis 2020.2 to access to the drivers generated, I am not able to build the project because there are some troubles with the makefile.

These are the errors generated:

Description Resource Path Location Type
make: *** missing separator. Stop. EclypseZ7_ZMOD_Platform line 24 C/C++ Problem
make[1]: *** [Makefile:42: ps7_cortexa9_0/libsrc/LFSR_v1_0/src/make.include] Error 2 EclypseZ7_ZMOD_Platform C/C++ Problem
make[1]: *** [Makefile:46: ps7_cortexa9_0/libsrc/LFSR_v1_0/src/make.libs] Error 2 EclypseZ7_ZMOD_Platform C/C++ Problem
make[2]: *** [Makefile:19: libs] Error 1 EclypseZ7_ZMOD_Platform C/C++ Problem

 

Could you please help me?

I have already tried this: https://www.xilinx.com/support/answers/75527.html

AND IT DID NOT WORK.

Thank you very much in advance.

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vras
Visitor
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732 Views
Registered: ‎12-22-2020

Dear all,

Finally, I found the mistake and got the SOLUTION,

Like some of you, I have had some troubles for compiling in Vitis 2020.2 with the Makefile of a Custom IP generated in VIVADO, everyone was saying that making some manually changes in the IP's Makefile the problems would be gone. However, no one said WHERE exactly the changes must be done, and for someone like me whit no to much expertise in Makefiles it is important to be clear in every single step...

Make sure the corrected makefile is replaced in three directories of the platform:

  1. Platform/hw/drivers/<CustomIP_name>/src/Makefile
  2. Platform/ps7_cortex_a9_0/standalone_domain/bsp/ps7_cortex_a9_0/libsrc/<CustomIP_name>/src/Makefile
  3. Platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortex_a9_0/libsrc/<CustomIP_name>/src/Makefile

After those three main changes your project will build Properly and your Custom IP will be working!

I attach the Makefile I've used so you all can reuse it, you just need to replace <CustomIP_name> for your Custom IP name, quite intuitive right..?

Thank you all, and wish you the best.

If this was helpful you could give me a Kudos, otherwise if you have still troubles, let me know and I will do my best to help you all.

View solution in original post

7 Replies
katsuki
Xilinx Employee
Xilinx Employee
1,055 Views
Registered: ‎11-05-2019

Hi @vras 

Maybe your Makefile has been modified incorrectly?
I've tried using Vivado's "Create and Package New IP" Wizard to create an AXI Lite Slave IP, modified the Makefile as you pointed out in AR#75527 and the build succeeds without any problems.

Thank you.
Don't forget to Reply, Kudo, and Accept as Solution.

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voroshazi
Observer
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1,004 Views
Registered: ‎10-10-2008

Dear vras,

I have this same annoying problem when creating a custom AXI-lite based IP in Vivado + VITIS 2020.2 by using Digilent Zybo platform.
It is still a Vivado-Vitis toolchain problem, because in 2020.1 the driver generation did not work, while in the latest 2020.2, there is still a problem with libraries during the compilation.
However, according to the answer record AR75527, the manual intervention into the driver's Makefile (location:  <wrapper>\ps7_cortexa9_0\standalone_ps7_cortexa9_0\bsp\ps7_cortexa9_0\libsrc\<your_custom_ip_name>\src\) can help if you use Vitis 2020.2. I tried it, and finally I successfully tested my custom IP.

Regards,

Zsolt

katsuki
Xilinx Employee
Xilinx Employee
921 Views
Registered: ‎11-05-2019

Hi @vras 

We've provided some information, if already issue has resolved, Kudo, and Accept as Solution.
If you have any questions, you can post them.

Thank you.
Don't forget to Reply, Kudo, and Accept as Solution.

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vras
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Registered: ‎12-22-2020

Dear @voroshazi

Everything is just as you said, however I tried to copy and use the makefile you provide me and I have still some errors. I do not know what else to do in order to get my custom IP working in Vitis2020.2.

These are the errors that are showing up right now:

Description Resource Path Location Type
make: *** [Makefile:18: all] Error 2 EclypseZ7_ZMOD_Platform C/C++ Problem
make: *** [Makefile:27: fsbl.elf] Error 1 EclypseZ7_ZMOD_Platform C/C++ Problem
make[1]: *** [Makefile:46: ps7_cortexa9_0/libsrc/LFSR_v1_0/src/make.libs] Error 2 EclypseZ7_ZMOD_Platform C/C++ Problem
make[2]: *** [Makefile:19: libs] Error 1 EclypseZ7_ZMOD_Platform C/C++ Problem

 

 

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vras
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Registered: ‎12-22-2020

Dear @katsuki 

Thank you for your response, but that does not work for me.

I have still the following errors:

Description Resource Path Location Type
make: *** [Makefile:18: all] Error 2 EclypseZ7_ZMOD_Platform C/C++ Problem
make: *** [Makefile:27: fsbl.elf] Error 1 EclypseZ7_ZMOD_Platform C/C++ Problem
make[1]: *** [Makefile:46: ps7_cortexa9_0/libsrc/LFSR_v1_0/src/make.libs] Error 2 EclypseZ7_ZMOD_Platform C/C++ Problem
make[2]: *** [Makefile:19: libs] Error 1 EclypseZ7_ZMOD_Platform C/C++ Problem

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vras
Visitor
Visitor
733 Views
Registered: ‎12-22-2020

Dear all,

Finally, I found the mistake and got the SOLUTION,

Like some of you, I have had some troubles for compiling in Vitis 2020.2 with the Makefile of a Custom IP generated in VIVADO, everyone was saying that making some manually changes in the IP's Makefile the problems would be gone. However, no one said WHERE exactly the changes must be done, and for someone like me whit no to much expertise in Makefiles it is important to be clear in every single step...

Make sure the corrected makefile is replaced in three directories of the platform:

  1. Platform/hw/drivers/<CustomIP_name>/src/Makefile
  2. Platform/ps7_cortex_a9_0/standalone_domain/bsp/ps7_cortex_a9_0/libsrc/<CustomIP_name>/src/Makefile
  3. Platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortex_a9_0/libsrc/<CustomIP_name>/src/Makefile

After those three main changes your project will build Properly and your Custom IP will be working!

I attach the Makefile I've used so you all can reuse it, you just need to replace <CustomIP_name> for your Custom IP name, quite intuitive right..?

Thank you all, and wish you the best.

If this was helpful you could give me a Kudos, otherwise if you have still troubles, let me know and I will do my best to help you all.

View solution in original post

pepijntje
Observer
Observer
605 Views
Registered: ‎01-10-2012

Dear Vras,

Vitis 2020.2 .... sigh sigh sigh

The solution with your modified makefile is working perfectly.  But for the ZynqMP :  only the cortexa53_0, 1 and 2.  No way to have the cortexa53_3 running.  Adding the a53_3 generates an error. Removing a53_3 is working.

Converting an existing design from Xilinx tools 2020.1 to tools 2020.2 is OK.  But once adding a new IP in 2020.2 :  nightmare ....

Any bright mind with a simple solution ?

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