06-12-2009 11:54 AM
In EDK 10.1 using Base System Builder, new design for custom board, there was an option to select SDR SDRAM. Now with EDK 11.1 I do not see that option.... only DDR and DDR2. Is Xilinx trying to tell me not to use SDR SDRAM in a new design, or am I expected to select DDR then change the mpmc core later to SDR ?
06-13-2009 09:21 AM
07-16-2009 10:41 AM
The Xilinx mpmc document says that SDR SDRAM is supported and explains how to use it (see link below) , so am proceeding with a design that uses it. In a few weeks I will be able to say for sure if it works ! One thing to note is that there is some complication with needing an extra clock and a DCM to generate it, and playing with the DCM phase shift to optimize timing. But I gather that if the SDRAM clock speed is low enough you can just go with a fixed phase extra clock. Even so I think it is still simpler than using a DDR SDRAM part. Plus it allows me to do everything with 3.3V.
For XPS, what helped was to create a custom board definition file "xbd file" for my proto board and specify SDR SDRAM in that. Then when I use Base System Builder I select my custom xbd file and XPS happily comes up with a SDRAM core, and generates a design using the pinout specified in my xbd file. There are some example xbd files around on the web. The xbd file made it easier to create a design with SDR SDRAM.