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Adventurer
Adventurer
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Registered: ‎10-11-2011

EDK 14.1: custom peripheral issues

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I built a custom peripheral and added it to EDK (14.1).  It didn't work as expected, so I tried to add chipscope to the core.  I generated a chipscope ILA and ICON in CoreGen, instantiated them in the peripheral HDL using the .veo templates, and went through the Import Peripheral wizard again so I could add the chipscope cores (as .ngc files) and make sure EDK would be able to see them.

 

However, EDK does not see the chipscope modules during synthesis and I get the following error:

 

ERROR:HDLCompiler:1654 - "/home/dvanarnem/devl/hsc/dsp/redundancy/hw/pcores/tr_adder_v1_00_a/hdl/verilog/tr_add.v" Line 44: Instantiating <icon> from unknown module <chipscope_icon>

 The same error occurs with the ILA if I remove the ICON.  I'm not sure why the chipscope components are not being seen, can anyone offer some suggestions?  I've attached the core's .mpd, .pao, and .bbd files (I removed the comment headers).  tr_adder is the name of my custom peripheral.

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Adventurer
Adventurer
5,423 Views
Registered: ‎10-11-2011

The solution seems to be adding a module declaration in addition to the instantiation, as specified in the XST User Guide Black Box section.  It's synthesizing now.  The .veo instantiation templates created by CoreGen didn't have the module declarations so I didn't think I needed them.

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Anonymous
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hi

why dont you add chipscope usind debug -> debug configuration menu? it's so easy

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Adventurer
Adventurer
4,231 Views
Registered: ‎10-11-2011

I can't get access to the signals I need to watch using the debug menu configuration.  I can only view the AXI slave signals; the signals I need are further down in the hierarchy of the core and don't show up in the debug configuration, even if I try the ILA option (in which case selecting my custom core doesn't show any signals I can monitor).

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Adventurer
Adventurer
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Registered: ‎10-11-2011

Also, everytime I open the project in XPS I get the following info messages from EDK:

 

INFO:EDK:4398 - file name is pcores/tr_adder_v1_00_a/netlist/chipscope_icon.ngc
INFO:EDK:4398 - file name is pcores/tr_adder_v1_00_a/netlist/chipscope_ila.ngc

 

I'm really hitting a wall here :-/

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Adventurer
Adventurer
5,424 Views
Registered: ‎10-11-2011

The solution seems to be adding a module declaration in addition to the instantiation, as specified in the XST User Guide Black Box section.  It's synthesizing now.  The .veo instantiation templates created by CoreGen didn't have the module declarations so I didn't think I needed them.

View solution in original post

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