cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
2,873 Views
Registered: ‎05-06-2014

EDK 14.4 clock_generator bug??

Jump to solution

I use XPS to build a ublaze system and two cascade clock_generators.

 

Two cascade clock_generators as belw:

uCLK clock signal is 50MHz from external pin.

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_1
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 166666666
 PARAMETER C_CLKOUT0_FREQ = 666666664
 PARAMETER C_CLKOUT0_PHASE = 337.5
 PARAMETER C_CLKOUT0_GROUP = PLLE0
 PARAMETER C_CLKOUT0_BUF = FALSE
 PARAMETER C_CLKOUT1_FREQ = 666666664
 PARAMETER C_CLKOUT1_GROUP = PLLE0
 PARAMETER C_CLKOUT1_BUF = FALSE
 PARAMETER C_CLKOUT2_FREQ = 41666666
 PARAMETER C_CLKOUT2_PHASE = 9.84375
 PARAMETER C_CLKOUT2_DUTY_CYCLE = 0.0625
 PARAMETER C_CLKOUT2_GROUP = PLLE0
 PARAMETER C_CLKOUT2_BUF = FALSE
 PARAMETER C_CLKOUT3_FREQ = 166666666
 PARAMETER C_CLKOUT3_GROUP = PLLE0
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT RST = RESET
 PORT CLKOUT0 = freq_refclk
 PORT CLKOUT1 = mem_refclk
 PORT CLKOUT2 = sync_pulse
 PORT CLKOUT3 = axi_clk_mm
 PORT CLKIN = clk_166_666MHz
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 166666666
 PARAMETER C_CLKOUT0_GROUP = PLLE0
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_GROUP = PLLE0
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_GROUP = PLLE0
 PARAMETER C_CLKOUT3_FREQ = 50000000
 PARAMETER C_CLKOUT3_GROUP = PLLE0
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT RST = RESET
 PORT CLKIN = uCLK
 PORT CLKOUT0 = clk_166_666MHz
 PORT CLKOUT1 = clk_200_0000MHzPLLE0
 PORT CLKOUT2 = clk_100_0000MHzPLLE0
 PORT CLKOUT3 = clk_50_0000MHzPLLE0
 PORT LOCKED = clock_generator_0_locked
END

 

 

XPS show error message and stop.

---------------------------------------------------------------------------------------------------------

IPNAME:clock_generator INSTANCE:clock_generator_0 -
C:\mcu.mhs line 140 - elaborating IP
ERROR:EDK:3900 - issued from TCL procedure "syslevel_update" line 48
   clock_generator_0 (clock_generator) - Clock generator failed to generate a
   clock circuit for the design clock_generator_0. For error analysis and hints
   to successfully generate the clock circuit, please refer to the file
   clock_generator_0.log in the project directory,
   C:/clock_generator_0.log
ERROR:EDK:440 - platgen failed with errors!
Done!
---------------------------------------------------------------------------------------------------------

 

------------------------------------------------------------------------------

-- clock_generator_0.log
------------------------------------------------------------------------------
Clock generation result : FAILED
------------------------------------------------------------------------------
C_FAMILY = kintex7
C_CLKIN_FREQ = 50000000
C_CLKFBIN_FREQ = 0
C_CLKFBOUT_FREQ = 0
C_CLKFBOUT_BUF = TRUE

C_CLKOUT0_FREQ = 166666666
C_CLKOUT0_PHASE = 0
C_CLKOUT0_GROUP = PLLE0
C_CLKOUT0_BUF = TRUE
C_CLKOUT0_VARIABLE_PHASE = FALSE

C_CLKOUT1_FREQ = 200000000
C_CLKOUT1_PHASE = 0
C_CLKOUT1_GROUP = PLLE0
C_CLKOUT1_BUF = TRUE
C_CLKOUT1_VARIABLE_PHASE = FALSE

C_CLKOUT2_FREQ = 100000000
C_CLKOUT2_PHASE = 0
C_CLKOUT2_GROUP = PLLE0
C_CLKOUT2_BUF = TRUE
C_CLKOUT2_VARIABLE_PHASE = FALSE

C_CLKOUT3_FREQ = 50000000
C_CLKOUT3_PHASE = 0
C_CLKOUT3_GROUP = PLLE0
C_CLKOUT3_BUF = TRUE
C_CLKOUT3_VARIABLE_PHASE = FALSE
------------------------------------------------------------------------------
ERROR:
CLKOUT0 can not be generated alone from the clock input

HINTS:

Change the clock's frequency and/or phase requirements,
  please refer to DC and Switching Characteristics for
  frequency range according to the device's family and
  speed grade
  the frequency gain between CLKOUT and CLKIN has to be:
  for DCM, M/D where M = 2 to 32 and D = 1 to 32, or
           1/D where D = 1.5, 2, 2.5, 3, 3.5, 4, 4,5, 5,
                         5.5, 6, 6.5, 7, 7.5, 8, 9, 10,
                         11, 12, 13, 14, 15, 16
  for PLL and MMCM, M/D/Dout where M = 1 to 64, D = 1 to 52 and
                          Dout = 1 to 128
  for phase shift requirements other than 0, 90, 180 and
  270, please refer to the Phase Shifting section of
  the device's User Guide about DCM, PLL and MMCM

 When PLLE0 is driving ddr memory controller, following M/D restrictions apply on mem_refclk:
 (frequency ranges are in MHz)
M=1 to 8
 D0=2                   400 <= mem-cntlr frequency <= 933
 D0=4                   200 <= mem-cntlr frequency < 400
 D=1,2,4
------------------------------------------------------------------------------
-- end of clock_generator_0.log
------------------------------------------------------------------------------

I don't know how to check this error from xilinx log file.

 

If I change uCLK from 50MHz to 100MHz, XPS will be passed and generate what I want.

 

What did happend XPS in this case?

 

In other way, I try to build two cascade clock_generators by coregen s/w is ISE.

In fortunately, there is no error when sythesized and P&R processing.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Visitor
Visitor
3,673 Views
Registered: ‎05-06-2014

Re: EDK 14.4 clock_generator bug??

Jump to solution

I try to modify the group of clock_generator_0 and re-build it.

--------------------------------------------------------------------

 PARAMETER C_CLKOUT0_FREQ = 166666666
 PARAMETER C_CLKOUT0_GROUP = NONE
--------------------------------------------------------------------

 

XPS will be passed.

 

The code of clock_generator_0 has two clock modules, mmcm for 166MHz output clock and plle2 for others output clock.

 

If I use clock_generator_0 code by coregen generated, it only has one plle2 for all output clocks.

 

I don't know what rules EDK check clock generation within?

View solution in original post

2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
2,864 Views
Registered: ‎08-02-2007

Re: EDK 14.4 clock_generator bug??

Jump to solution

Hi,

 

Would that be possible to use different groups for each of the clocks? It looks that you are using the same PLLE0 for deriving all the clock outputs.

 

 PARAMETER C_CLKOUT1_GROUP = PLLE0

--Hem

 

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
3,674 Views
Registered: ‎05-06-2014

Re: EDK 14.4 clock_generator bug??

Jump to solution

I try to modify the group of clock_generator_0 and re-build it.

--------------------------------------------------------------------

 PARAMETER C_CLKOUT0_FREQ = 166666666
 PARAMETER C_CLKOUT0_GROUP = NONE
--------------------------------------------------------------------

 

XPS will be passed.

 

The code of clock_generator_0 has two clock modules, mmcm for 166MHz output clock and plle2 for others output clock.

 

If I use clock_generator_0 code by coregen generated, it only has one plle2 for all output clocks.

 

I don't know what rules EDK check clock generation within?

View solution in original post