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navi_gator
Newbie
Newbie
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Registered: ‎04-15-2019

EDK:3458 invalid clock frequencies ratio for ports clk and clk_mem

I am using Xilinx Platform Studio Version 14.7, for a Perseus6013(Virtex6)

When generating a bitstream to an extensive already existing Project that should compile without a problem, I get the error:

ERROR:EDK:3458 - In the core DDR3_SDRAM, the ratio of clock frequencies is invalid for the ports clk and clk_mem
ERROR:EDK:3365 - Clock frequency ratio requirements not met in IP : DDR3_SDRAM

 

 

There is a similar problem with a patch and old solution regarding a Virtex7

https://www.xilinx.com/support/answers/51151.html

also stating that the problem should be fixed in versions 12.3 and higher.

is there a patch for the virtex6?

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stephenm
Moderator
Moderator
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Registered: ‎09-12-2007

Can you share the MHS file?

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