I am using Xilinx Platform Studio Version 14.7, for a Perseus6013(Virtex6)
When generating a bitstream to an extensive already existing Project that should compile without a problem, I get the error:
ERROR:EDK:3458 - In the core DDR3_SDRAM, the ratio of clock frequencies is invalid for the ports clk and clk_memERROR:EDK:3365 - Clock frequency ratio requirements not met in IP : DDR3_SDRAM
There is a similar problem with a patch and old solution regarding a Virtex7
also stating that the problem should be fixed in versions 12.3 and higher.
is there a patch for the virtex6?
Can you share the MHS file?