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Visitor akur061
Visitor
3,209 Views
Registered: ‎07-03-2011

EDK LUT mapping failure. MapLib:979 - LUT3 symbol error

Hello, 

I have recently made a project which uses two AXI masters to interact with two BRAM controllers in Xilinx EDK. When I try generating a bit file, the program fails during the mapping phase in which maps the designs to the LUTs.

 

The 5 errors, I've received are as followed .

ERROR:MapLib:979 - LUT3 symbol

ERROR:MapLib:979 - LUT3 symbol

ERROR:MapLib:979 - LUT6 symbol

ERROR:MapLib:978 - LUT3 symbol

ERROR:MapLib:978 - LUT6 symbol

 

Does anyone have any suggestions on what may be causing these errors? I have also included a more detailed error report below.

 

Thanks for reading,

A


 


ERROR:MapLib:979 - LUT3 symbol
"axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_a sync_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite_ch.gw ach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_60_dpot" (output
signal=axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst
/gen_async_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite
_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_60_dpot) has
input signal
"axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_a
sync_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite_ch.gw
ach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014<60>" which will be
trimmed. See Section 5 of the Map Report File for details about why the input
signal will become undriven.
ERROR:MapLib:979 - LUT3 symbol
"axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_a sync_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite_ch.gw ach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_61_dpot" (output
signal=axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst
/gen_async_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite
_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_61_dpot) has
input signal
"axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_a
sync_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite_ch.gw
ach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014<61>" which will be
trimmed. See Section 5 of the Map Report File for details about why the input
signal will become undriven.
ERROR:MapLib:979 - LUT6 symbol
"axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_a sync_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite_ch.gw dch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36_dpot1" (output
signal=axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst
/gen_async_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite
_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36_dpot1) has
input signal
"axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_a
sync_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite_ch.gw
dch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/_n0014<36>" which will be
trimmed. See Section 5 of the Map Report File for details about why the input
signal will become undriven.
WARNING:MapLib:701 - Signal RS232_Uart_1_sin connected to top level port
RS232_Uart_1_sin has been removed.
ERROR:MapLib:978 - LUT3 symbol
"axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_a sync_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite_ch.gw ach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_60_dpot" (output
signal=axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst
/gen_async_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite
_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_60_dpot) has
an equation that uses input pin I2, which no longer has a connected signal.
Please ensure that all the pins used in the equation for this LUT have
signals that are not trimmed (see Section 5 of the Map Report File for
details on which signals were trimmed).
ERROR:MapLib:978 - LUT3 symbol
"axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_a sync_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite_ch.gw ach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_61_dpot" (output
signal=axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst
/gen_async_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite
_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_61_dpot) has
an equation that uses input pin I2, which no longer has a connected signal.
Please ensure that all the pins used in the equation for this LUT have
signals that are not trimmed (see Section 5 of the Map Report File for
details on which signals were trimmed).
ERROR:MapLib:978 - LUT6 symbol
"axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_a sync_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite_ch.gw dch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36_dpot1" (output
signal=axi_i_bus/axi_i_bus/si_converter_bank/gen_conv_slot[0].clock_conv_inst
/gen_async_readwrite.asyncfifo_rw/U0/xst_fifo_generator/gaxi_full_lite.gwrite
_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36_dpot1) has
an equation that uses input pin I5, which no longer has a connected signal.
Please ensure that all the pins used in the equation for this LUT have
signals that are not trimmed (see Section 5 of the Map Report File for
details on which signals were trimmed).
WARNING:MapLib:41 - All members of TNM group
"TNM_TIG_DDR3_SDRAM_IODELAY_CTRL_RDY_O_SYNCH" have been optimized out of the
design.
WARNING:MapLib:41 - All members of TNM group
"TNM_TIG_DDR3_SDRAM_IODELAY_CTRL_RST_SYNCH" have been optimized out of the
design.
WARNING:MapLib:48 - The timing specification
"TS_TIG_DDR3_SDRAM_IODELAY_CTRL_RDY_O_SYNCH" has been discarded because its
TO group (TNM_TIG_DDR3_SDRAM_IODELAY_CTRL_RDY_O_SYNCH) was optimized away.
WARNING:MapLib:48 - The timing specification
"TS_TIG_DDR3_SDRAM_IODELAY_CTRL_RST_SYNCH" has been discarded because its TO
group (TNM_TIG_DDR3_SDRAM_IODELAY_CTRL_RST_SYNCH) was optimized away.

Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.

Design Summary
--------------
Number of errors : 6
Number of warnings : 5
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
Done!

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2 Replies
Visitor akur061
Visitor
3,208 Views
Registered: ‎07-03-2011

Re: EDK LUT mapping failure. MapLib:979 - LUT3 symbol error

I should also add that the Board I'm using is a Xilinx Virtex 6 ML605.
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Voyager
Voyager
3,180 Views
Registered: ‎04-10-2012

Re: EDK LUT mapping failure. MapLib:979 - LUT3 symbol error

I am having a similar issue.  Everything was fine until I starting playing with Plan Ahead and then opened up the core to make a change, now it wouldgenerate the BitStream...

 

I am using a custom board with a Virtex-6

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