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Observer
Observer
10,889 Views
Registered: ‎05-28-2009

EDK Peripheral reads always return 0.

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I have a custom peripheral, using a plb_slave_single_v1_00_a component, originally generated with the wizard.  Writes work fine, but reads always return zero.  I have a chipscope in my peripheral which picks up the read returning the correct data with a one clock cycle readack, attached screenshot below.   mrd's to the peripheral return zero, as does access from software.

 

What could be wrong?

 

Message Edited by rburns on 06-08-2009 04:33 PM
edk_read.jpg
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Observer
Observer
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Registered: ‎05-28-2009
I had made the peripheral in 10.1, and am now using 11.1.  I pointed the peripheral to the latest versions of proc_common and plb_slave_single in the 11.1 installation directory and rebuilt, and this resolved the problem.

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Historian
Historian
10,868 Views
Registered: ‎02-25-2008

Is there a pipeline delay in the mux that drives IP2Bus_Data? You show us cpu_readdata but not IP2Bus_Data.

 

-a

----------------------------Yes, I do this for a living.
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Observer
Observer
10,865 Views
Registered: ‎05-28-2009
No, cpu_readdata is connected directly to ipif_IP2Bus_Data in the wizard file which contains my user logic instance and the plbv46_slave_single_v1_00_a instance.  The chipscope is in my user logic, hence the signal name.
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Xilinx Employee
Xilinx Employee
10,856 Views
Registered: ‎08-07-2007
Try BFM simulation.
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Observer
Observer
13,078 Views
Registered: ‎05-28-2009
I had made the peripheral in 10.1, and am now using 11.1.  I pointed the peripheral to the latest versions of proc_common and plb_slave_single in the 11.1 installation directory and rebuilt, and this resolved the problem.

View solution in original post

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Observer
Observer
10,836 Views
Registered: ‎10-27-2008

I have the same problem. The details are:

 

Tool: XPS 10.1.03

 

microblaze 7.10.d

PLB: 1.03.a

my IP was : proc_common v2.0.a/plb_slave-single v1.00.a

          changed to : proc_common v3.0.a /plb_slave_single v1.01.a

 

This didn't fix my problem. I can not only see the data on IP2Bus_Data in chipscope but I can see the FPGA outputs on my scope so the data is certainly getting into the ram but it doesn't seem to be getting back to the microblaze. Using the memory viewer in the debugger one reads only zeros from the IP core. Any thoughts?

 

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Observer
Observer
10,826 Views
Registered: ‎05-28-2009

You also have a readack?

 

For reference, I am using 11.1, microblaze_0 7.20.a, plb 1.04.a

 

I fixed it by doing the  same upgrade as you:

proc_common v2.0.a/plb_slave-single v1.00.a

          changed to : proc_common v3.0.a /plb_slave_single v1.01.a

 

The other thing I was in the midst of doing when I got it working, was to make a new test peripheral with the wizard with a single register, and then going into the user logic and having the register reset to a non-zero value.  I was going to see if I could read that register.  You could try this.

 

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Observer
Observer
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Registered: ‎10-27-2008

There is indeed a readback. In fact the memory space cs[0] is decoded into 16 32bit registers at { baseaddr .. basedaddr + 0x40] and a2kx32 true dual port block ram at baseaddr + 0x2000. The 16 registers write and readback correctly using cs&rnw&(address space == registers space) as read acknowledge and a delayed read acknowledge for the block ram = delayed( cs&rnw&(address space is in blockram address space )  ). The two read acknowledge signals are or'ed together and look correct on chipscope but I notice that the cs, rnw, be, and address signals from the slave decoder don't get 'stretched' by the delay as they are shown in the slave single datasheet. The timing diagram in the datasheet leads one to believe that those bus signals will be held until ack is asserted ( or the dataphase timer times out).

I am suspicious that you are using plb v1.04, unfortunately I don't see it in EDK 10.1.03.

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Observer
Observer
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Registered: ‎10-27-2008
Check that. I just rebuilt after 'cleaning hardware' and now the IP core is reading back correctly. I know that the IP core rebuilt with the upgrades to proc_common and slave_single without fixing the problem so I suspect there was an incompatibility with the earlier version of the plb. Who knows, this is EDK, a world shrouded in mystery.
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7,185 Views
Registered: ‎01-28-2011

Unfortunately, when I use microblaze(v7.20.d) and EPC(v1.02) In ISE11.4, I also have the same problem.

 

the chip select signal  and the read signal rise at the same time in the read process.

 

I change my ISE version to v12.3 and V10.1, the problem still exists.

 I am sure that the configuration of EPC is ok. The same parameters was used in the last projects.

 

If I change the pin assignments somewhere , the problem is fixed.

 

I doubt the problem is related to the implentment of ISE projects.

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