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Registered: ‎06-21-2013

EDK XPS error 4207,4208,4209. SD card problem

I encountered some problems when I using my XPS tool ver.14.4.

I use Kintex-7 board (KC705) with embedded kit. That kit provides SD Card IP from 3rd party(xylon). So When I 

attached the IP with microblaze in XPS some errors are occured below. Somebody know how can I solved it?

 

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ERROR:EDK:4207 - TRI_I sub-property is not present on tri-state port sd_dat. MPD must not contain port with name sd_dat_I
ERROR:EDK:4208 - TRI_O sub-property is not present on tri-state port sd_dat. MPD must not contain port with name sd_dat_O
ERROR:EDK:4209 - TRI_T sub-property is not present on tri-state port sd_dat. MPD must not contain port with name sd_dat_T
ERROR:EDK:4207 - TRI_I sub-property is not present on tri-state port sd_cmd. MPD must not contain port with name sd_cmd_I
ERROR:EDK:4208 - TRI_O sub-property is not present on tri-state port sd_cmd. MPD must not contain port with name sd_cmd_O
ERROR:EDK:4209 - TRI_T sub-property is not present on tri-state port sd_cmd. MPD must not contain port with name sd_cmd_T

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Here is my MHS file

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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.4 Build EDK_P.49d
# Mon Jun 17 16:23:30 2013
# Target Board: xilinx.com kc705 Rev C
# Family: kintex7
# Device: xc7k325t
# Package: ffg900
# Speed Grade: -2
# ##############################################################################
PARAMETER VERSION = 2.1.0


PORT sm_fan_pwm_net_vcc = net_vcc, DIR = O
PORT ddr_memory_we_n = ddr_memory_we_n, DIR = O
PORT ddr_memory_ras_n = ddr_memory_ras_n, DIR = O
PORT ddr_memory_odt = ddr_memory_odt, DIR = O
PORT ddr_memory_dqs_n = ddr_memory_dqs_n, DIR = IO, VEC = [0:0]
PORT ddr_memory_dqs = ddr_memory_dqs, DIR = IO, VEC = [0:0]
PORT ddr_memory_dq = ddr_memory_dq, DIR = IO, VEC = [7:0]
PORT ddr_memory_dm = ddr_memory_dm, DIR = O, VEC = [0:0]
PORT ddr_memory_ddr3_rst = ddr_memory_ddr3_rst, DIR = O
PORT ddr_memory_cs_n = ddr_memory_cs_n, DIR = O
PORT ddr_memory_clk_n = ddr_memory_clk_n, DIR = O, SIGIS = CLK
PORT ddr_memory_clk = ddr_memory_clk, DIR = O, SIGIS = CLK
PORT ddr_memory_cke = ddr_memory_cke, DIR = O
PORT ddr_memory_cas_n = ddr_memory_cas_n, DIR = O
PORT ddr_memory_ba = ddr_memory_ba, DIR = O, VEC = [2:0]
PORT ddr_memory_addr = ddr_memory_addr, DIR = O, VEC = [13:0]
PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
PORT Push_Buttons_5Bits_TRI_I = Push_Buttons_5Bits_TRI_I, DIR = I, VEC = [4:0]
PORT LEDs_8Bits_TRI_O = LEDs_8Bits_TRI_O, DIR = O, VEC = [7:0]
PORT IIC_MAIN_SDA = IIC_MAIN_SDA, DIR = IO
PORT IIC_MAIN_SCL = IIC_MAIN_SCL, DIR = IO
PORT Ethernet_Lite_TX_EN = Ethernet_Lite_TX_EN, DIR = O
PORT Ethernet_Lite_TX_CLK = Ethernet_Lite_TX_CLK, DIR = I
PORT Ethernet_Lite_TXD = Ethernet_Lite_TXD, DIR = O, VEC = [3:0]
PORT Ethernet_Lite_RX_ER = Ethernet_Lite_RX_ER, DIR = I
PORT Ethernet_Lite_RX_DV = Ethernet_Lite_RX_DV, DIR = I
PORT Ethernet_Lite_RX_CLK = Ethernet_Lite_RX_CLK, DIR = I
PORT Ethernet_Lite_RXD = Ethernet_Lite_RXD, DIR = I, VEC = [3:0]
PORT Ethernet_Lite_PHY_RST_N = Ethernet_Lite_PHY_RST_N, DIR = O
PORT Ethernet_Lite_MDIO = Ethernet_Lite_MDIO, DIR = IO
PORT Ethernet_Lite_MDC = Ethernet_Lite_MDC, DIR = O
PORT Ethernet_Lite_CRS = Ethernet_Lite_CRS, DIR = I
PORT Ethernet_Lite_COL = Ethernet_Lite_COL, DIR = I
PORT DIP_Switches_TRI_I = DIP_Switches_TRI_I, DIR = I, VEC = [3:0]
PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
PORT logisdhc_0_sd_clk_pin = logisdhc_0_sd_clk, DIR = O, SIGIS = CLK
PORT logisdhc_0_sd_dat_pin = logisdhc_0_sd_dat, DIR = IO, VEC = [3:0]
PORT logisdhc_0_sd_cmd_pin = logisdhc_0_sd_cmd, DIR = IO
PORT logisdhc_0_sd_led_n_pin = logisdhc_0_sd_led_n, DIR = O
PORT logisdhc_0_sd_base_lock_pin = net_logisdhc_0_sd_base_lock_pin, DIR = I


BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT MB_Reset = proc_sys_reset_0_MB_Reset
PORT Slowest_sync_clk = clk_100_0000MHzPLLE0
PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
PORT Ext_Reset_In = RESET
PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
PORT Peripheral_Reset = proc_sys_reset_0_Peripheral_Reset
PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
END

# PORT Dcm_locked = logisdhc_0_sd_base_rst
BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_ilmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
PORT LMB_CLK = clk_100_0000MHzPLLE0
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = microblaze_0_ilmb
BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_dlmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
PORT LMB_CLK = clk_100_0000MHzPLLE0
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = microblaze_0_dlmb
BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
PARAMETER INSTANCE = microblaze_0_bram_block
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 8.40.b
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0xc0000000
PARAMETER C_ICACHE_HIGHADDR = 0xc7ffffff
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 8192
PARAMETER C_ICACHE_ALWAYS_USED = 1
PARAMETER C_DCACHE_BASEADDR = 0xc0000000
PARAMETER C_DCACHE_HIGHADDR = 0xc7ffffff
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 8192
PARAMETER C_DCACHE_ALWAYS_USED = 1
PARAMETER C_FSL_LINKS = 2
PARAMETER C_STREAM_INTERCONNECT = 0
BUS_INTERFACE M_AXI_DP = axi4lite_0
BUS_INTERFACE M_AXI_DC = axi4_0
BUS_INTERFACE M_AXI_IC = axi4_0
BUS_INTERFACE DEBUG = microblaze_0_debug
BUS_INTERFACE MFSL0 = fsl_v20_0
BUS_INTERFACE SFSL1 = fsl_v20_1
BUS_INTERFACE DLMB = microblaze_0_dlmb
BUS_INTERFACE ILMB = microblaze_0_ilmb
PORT MB_RESET = proc_sys_reset_0_MB_Reset
PORT CLK = clk_100_0000MHzPLLE0
END

BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.10.a
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_UART = 1
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT S_AXI_ACLK = clk_100_0000MHzPLLE0
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_CLKIN_FREQ = 200000000
PARAMETER C_CLKOUT0_FREQ = 400000000
PARAMETER C_CLKOUT0_PHASE = 337.5
PARAMETER C_CLKOUT0_GROUP = PLLE0
PARAMETER C_CLKOUT0_BUF = FALSE
PARAMETER C_CLKOUT1_FREQ = 400000000
PARAMETER C_CLKOUT1_GROUP = PLLE0
PARAMETER C_CLKOUT1_BUF = FALSE
PARAMETER C_CLKOUT2_FREQ = 25000000
PARAMETER C_CLKOUT2_PHASE = 9.84375
PARAMETER C_CLKOUT2_DUTY_CYCLE = 0.0625
PARAMETER C_CLKOUT2_GROUP = PLLE0
PARAMETER C_CLKOUT2_BUF = FALSE
PARAMETER C_CLKOUT3_FREQ = 100000000
PARAMETER C_CLKOUT3_GROUP = PLLE0
PARAMETER C_CLKOUT4_FREQ = 200000000
PARAMETER C_CLKOUT4_GROUP = PLLE0
PORT LOCKED = proc_sys_reset_0_Dcm_locked
PORT CLKOUT3 = clk_100_0000MHzPLLE0
PORT RST = RESET
PORT CLKOUT2 = clk_25_0000MHz9.84375PLLE0_nobuf
PORT CLKOUT1 = clk_400_0000MHzPLLE0_nobuf
PORT CLKOUT0 = clk_400_0000MHz337.5PLLE0_nobuf
PORT CLKOUT4 = clk_200_0000MHzPLLE0
END

BEGIN axi_interconnect
PARAMETER INSTANCE = axi4lite_0
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
PORT INTERCONNECT_ACLK = clk_100_0000MHzPLLE0
END

BEGIN axi_interconnect
PARAMETER INSTANCE = axi4_0
PARAMETER HW_VER = 1.06.a
PORT interconnect_aclk = clk_100_0000MHzPLLE0
PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.02.a
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 1
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHzPLLE0
PORT TX = RS232_Uart_1_sout
PORT RX = RS232_Uart_1_sin
END

BEGIN axi_gpio
PARAMETER INSTANCE = Push_Buttons_5Bits
PARAMETER HW_VER = 1.01.b
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHzPLLE0
PORT GPIO_IO_I = Push_Buttons_5Bits_TRI_I
END

BEGIN axi_gpio
PARAMETER INSTANCE = LEDs_8Bits
PARAMETER HW_VER = 1.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x4002ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHzPLLE0
PORT GPIO_IO_O = LEDs_8Bits_TRI_O
END

BEGIN axi_iic
PARAMETER INSTANCE = IIC_MAIN
PARAMETER HW_VER = 1.02.a
PARAMETER C_IIC_FREQ = 100000
PARAMETER C_TEN_BIT_ADR = 0
PARAMETER C_BASEADDR = 0x40800000
PARAMETER C_HIGHADDR = 0x4080ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHzPLLE0
PORT Sda = IIC_MAIN_SDA
PORT Scl = IIC_MAIN_SCL
END

BEGIN axi_ethernetlite
PARAMETER INSTANCE = Ethernet_Lite
PARAMETER HW_VER = 1.01.b
PARAMETER C_BASEADDR = 0x40e00000
PARAMETER C_HIGHADDR = 0x40e0ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHzPLLE0
PORT PHY_tx_en = Ethernet_Lite_TX_EN
PORT PHY_tx_clk = Ethernet_Lite_TX_CLK
PORT PHY_tx_data = Ethernet_Lite_TXD
PORT PHY_rx_er = Ethernet_Lite_RX_ER
PORT PHY_dv = Ethernet_Lite_RX_DV
PORT PHY_rx_clk = Ethernet_Lite_RX_CLK
PORT PHY_rx_data = Ethernet_Lite_RXD
PORT PHY_rst_n = Ethernet_Lite_PHY_RST_N
PORT PHY_MDIO = Ethernet_Lite_MDIO
PORT PHY_MDC = Ethernet_Lite_MDC
PORT PHY_crs = Ethernet_Lite_CRS
PORT PHY_col = Ethernet_Lite_COL
END

BEGIN axi_gpio
PARAMETER INSTANCE = DIP_Switches_8Bits
PARAMETER HW_VER = 1.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER C_BASEADDR = 0x40040000
PARAMETER C_HIGHADDR = 0x4004ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHzPLLE0
PORT GPIO_IO_I = DIP_Switches_TRI_I
END

BEGIN axi_7series_ddrx
PARAMETER INSTANCE = DDR3_SDRAM
PARAMETER HW_VER = 1.07.a
PARAMETER C_MEM_PARTNO = CUSTOM
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
PARAMETER C_DM_WIDTH = 1
PARAMETER C_DQS_WIDTH = 1
PARAMETER C_DQ_WIDTH = 8
PARAMETER C_ROW_WIDTH = 14
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
PARAMETER C_MEM_BASEPARTNO = MT8JTF12864HZ-1G6
PARAMETER C_S_AXI_BASEADDR = 0xc0000000
PARAMETER C_S_AXI_HIGHADDR = 0xc7ffffff
BUS_INTERFACE S_AXI = axi4_0
PORT clk = clk_100_0000MHzPLLE0
PORT ddr_we_n = ddr_memory_we_n
PORT ddr_ras_n = ddr_memory_ras_n
PORT ddr_odt = ddr_memory_odt
PORT ddr_dqs_n = ddr_memory_dqs_n
PORT ddr_dqs_p = ddr_memory_dqs
PORT ddr_dq = ddr_memory_dq
PORT ddr_dm = ddr_memory_dm
PORT ddr_reset_n = ddr_memory_ddr3_rst
PORT ddr_cs_n = ddr_memory_cs_n
PORT ddr_ck_n = ddr_memory_clk_n
PORT ddr_ck_p = ddr_memory_clk
PORT ddr_cke = ddr_memory_cke
PORT ddr_cas_n = ddr_memory_cas_n
PORT ddr_ba = ddr_memory_ba
PORT ddr_addr = ddr_memory_addr
PORT sync_pulse = clk_25_0000MHz9.84375PLLE0_nobuf
PORT mem_refclk = clk_400_0000MHzPLLE0_nobuf
PORT freq_refclk = clk_400_0000MHz337.5PLLE0_nobuf
PORT clk_ref = clk_200_0000MHzPLLE0
PORT pll_lock = proc_sys_reset_0_Dcm_locked
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_0
PARAMETER HW_VER = 2.11.f
PARAMETER C_USE_CONTROL = 0
PORT FSL_Clk = clk_100_0000MHzPLLE0
PORT SYS_Rst = proc_sys_reset_0_Peripheral_Reset
END

BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_1
PARAMETER HW_VER = 2.11.f
PARAMETER C_USE_CONTROL = 0
PORT FSL_Clk = clk_100_0000MHzPLLE0
PORT SYS_Rst = proc_sys_reset_0_Peripheral_Reset
END

BEGIN msr_top
PARAMETER INSTANCE = msr_top_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE SFSL = fsl_v20_0
BUS_INTERFACE MFSL = fsl_v20_1
END

BEGIN logisdhc
PARAMETER INSTANCE = logisdhc_0
PARAMETER HW_VER = 1.07.a
PARAMETER C_REGS_BASEADDR = 0x72e00000
PARAMETER C_REGS_HIGHADDR = 0x72e0ffff
PARAMETER C_USE_DMA = 0
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHzPLLE0
PORT M_AXI_ACLK = clk_100_0000MHzPLLE0
PORT sd_clk = logisdhc_0_sd_clk
PORT sd_dat = logisdhc_0_sd_dat
PORT sd_cmd = logisdhc_0_sd_cmd
PORT sd_led_n = logisdhc_0_sd_led_n
PORT sd_base_clk = clk_100_0000MHzPLLE0
PORT sd_base_lock = proc_sys_reset_0_Dcm_locked
END

# PORT sd_cd_n = logisdhc_0_sd_base_rst_0

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Here is my MPD file for sdcard

------------------------------------------------------------------------------------------------------------------------------------------------------------------

###################################################################
##
## Name : logisdhc
## Desc : Microprocessor Peripheral Description
##
###################################################################

BEGIN logisdhc

## Peripheral Options
OPTION RUN_NGCBUILD = TRUE
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION USAGE_LEVEL = BASE_USER
OPTION IP_GROUP = logicBRICKS
OPTION ARCH_SUPPORT_MAP = (others=PRODUCTION)
OPTION DESC = Xylon SD Host Controller
OPTION LONG_DESC = logiSDHC is Xylon SD Host Controller. Please contact Xylon for further details.

## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE, EXCLUDE_BUSIF = (SPLB || S_AXI), ISVALID = (C_REGS_INTERFACE == 0)
BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE, EXCLUDE_BUSIF = (SOPB || S_AXI), ISVALID = (C_REGS_INTERFACE == 1)
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE, EXCLUDE_BUSIF = (SPLB || SOPB), ISVALID = (C_REGS_INTERFACE == 2)
BUS_INTERFACE BUS = XMB, BUS_TYPE = INITIATOR, EXCLUDE_BUSIF = (M_AXI), BUS_STD = XMB, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 1)
BUS_INTERFACE BUS = M_AXI, BUS_TYPE = MASTER, EXCLUDE_BUSIF = (XMB), BUS_STD = AXI, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)

## Generics for VHDL or Parameters for Verilog
########## IP Version generics ##########
PARAMETER C_IP_LICENSE_TYPE = 1, DT = INTEGER, RANGE = (0:2), VALUES = (0=source,1=evaluation,2=release), ISVALID = (0==1)
PARAMETER C_IP_MAJOR_REVISION = 1, DT = INTEGER, RANGE = (0:31), ISVALID = (0==1)
PARAMETER C_IP_MINOR_REVISION = 07, DT = INTEGER, RANGE = (0:31), ISVALID = (0==1)
PARAMETER C_IP_PATCH_LEVEL = 0, DT = INTEGER, RANGE = (0:25), VALUES = (0=a,1=b,2=c,3=d,4=e,5=f,6=g,7=h,8=i,9=j,10=k,11=l,12=m,13=n,14=o,15=p,16=q,17=r,18=s,19=t,20=u,21=v,22=w,23=x,24=y,25=z), ISVALID = (0==1)
PARAMETER C_IP_LICENSE_CHECK = 1, DT = INTEGER, RANGE = (0:1), VALUES = (0=No,1=Yes), ISVALID = (0==1)
########## Registers ##########
PARAMETER C_REGS_INTERFACE = 2, DT = integer, RANGE = (0,1,2), VALUES = (0=OPB, 1=PLB, 2=AXI4-Lite)
PARAMETER C_REGS_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0xFF, BUS = SOPB:SPLB:S_AXI, ADDRESS = BASE, PAIR = C_REGS_HIGHADDR, PERMIT = BASE_USER
PARAMETER C_REGS_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB:SPLB:S_AXI, ADDRESS = HIGH, PAIR = C_REGS_BASEADDR, PERMIT = BASE_USER
## OPB generics
PARAMETER C_OPB_DWIDTH = 32, DT = integer, ISVALID = (C_REGS_INTERFACE == 0)
PARAMETER C_OPB_AWIDTH = 32, DT = integer, ISVALID = (C_REGS_INTERFACE == 0)
## PLB Slave generics
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT, ISVALID = (C_REGS_INTERFACE == 1)
PARAMETER C_SPLB_DWIDTH = 32, DT = INTEGER, BUS = SPLB, ISVALID = (C_REGS_INTERFACE == 1)
PARAMETER C_SPLB_MID_WIDTH = 1, DT = INTEGER, BUS = SPLB, ISVALID = (C_REGS_INTERFACE == 1)
PARAMETER C_SPLB_NUM_MASTERS = 2, DT = INTEGER, BUS = SPLB, ISVALID = (C_REGS_INTERFACE == 1)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT, ISVALID = (C_REGS_INTERFACE == 1)
## AXI4-Lite Slave generics
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT, ISVALID = (C_REGS_INTERFACE == 2)
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT, ISVALID = (C_REGS_INTERFACE == 2)
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, DT = STRING, BUS = S_AXI, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, ISVALID = (C_REGS_INTERFACE == 2)
########## DMA Generics ##########
PARAMETER C_USE_DMA = 1, DT = INTEGER, RANGE = (0,1)
PARAMETER C_DMA_TYPE = 1, DT = INTEGER, RANGE = (0,1), VALUES = (0=standard DMA, 1=XYLON type DMA), ISVALID = (C_USE_DMA == 1)
PARAMETER C_MEM_INTERFACE = 2, DT = INTEGER, RANGE = (1,2), VALUES = (1=XMB, 2=AXI), ISVALID = (C_USE_DMA == 1)
PARAMETER C_MEM_BASEADDR = 0xffffffff, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_MEM_HIGHADDR, ADDR_TYPE = MEMORY, PERMIT = BASE_USER, ISVALID = (C_USE_DMA == 1)#,BUS = XMB:M_AXI
PARAMETER C_MEM_HIGHADDR = 0x00000000, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_MEM_BASEADDR, ADDR_TYPE = MEMORY, PERMIT = BASE_USER, ISVALID = (C_USE_DMA == 1)#,BUS = XMB:M_AXI
PARAMETER C_MEM_BURST = 4, DT = INTEGER, RANGE = (4,5,6), VALUES = (4=16,5=32,6=64), ISVALID = (C_USE_DMA == 1 && (C_MEM_INTERFACE == 1 || C_MEM_INTERFACE == 2))
## XMB generics
PARAMETER C_MEM_DATA_BUS_WIDTH = 32, DT = INTEGER, RANGE = (32), PERMIT = BASE_USER, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 1)
## AXI Master generics
PARAMETER C_M_AXI_SUPPORTS_THREADS = 0, DT = integer, BUS = M_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)
PARAMETER C_M_AXI_THREAD_ID_WIDTH = 1, DT = integer, BUS = M_AXI, ASSIGNMENT = CONSTANT, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)
PARAMETER C_M_AXI_SUPPORTS_READ = 1, DT = integer, BUS = M_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)
PARAMETER C_M_AXI_SUPPORTS_WRITE = 1, DT = integer, BUS = M_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)
PARAMETER C_M_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, BUS = M_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)
PARAMETER C_M_AXI_DATA_WIDTH = 32, DT = integer, RANGE = (32), BUS = M_AXI, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)
PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = integer, RANGE = (32), BUS = M_AXI, ASSIGNMENT = CONSTANT, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)
PARAMETER C_M_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = M_AXI, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)
PARAMETER C_INTERCONNECT_M_AXI_ARB_PRIORITY = 0, DT = integer, BUS = M_AXI, RANGE = (0:15), TYPE = NON_HDL, ISVALID = (C_USE_DMA == 1 && C_MEM_INTERFACE == 2)
##PARAMETER C_DMA_USE_BRAM = 1, DT = INTEGER, RANGE = (0,1), ISVALID = (C_USE_DMA == 1) => not implemented in this version
PARAMETER C_CONVERT_ENDIANESS = 0, DT = INTEGER, RANGE = (0,1), VALUES = (0=NO, 1=YES), ISVALID = (C_USE_DMA == 1 && C_DMA_TYPE == 1)
PARAMETER C_BYTE_PER_PIXEL = 4, DT = INTEGER, RANGE = (4), ISVALID = (C_USE_DMA == 1 && C_DMA_TYPE == 1)
PARAMETER C_ROW_STRIDE = 1024, DT = INTEGER, RANGE = (512, 1024, 2048), ISVALID = (C_USE_DMA == 1 && C_DMA_TYPE == 1)
########## SD Host generics ##########
PARAMETER C_FAMILY = spartan3:spartan3a:spartan3an:spartan3e:spartan6:virtex4:virtex5:virtex6:virtex7:kintex7, DT = STRING
PARAMETER C_SD_BASE_CLOCK_FREQ = 100, DT = INTEGER, CLK_PORT = sd_base_clk, CLK_UNIT = MHZ

## OPB Ports
PORT OPB_Clk = "", DIR = IN, SIGIS = CLK, BUS = SOPB
PORT OPB_Rst = OPB_Rst, DIR = IN, BUS = SOPB
PORT OPB_ABus = OPB_ABus, DIR = IN, VEC = [0:C_OPB_AWIDTH-1], BUS = SOPB
PORT OPB_BE = OPB_BE, DIR = IN, VEC = [0:C_OPB_DWIDTH/8-1], BUS = SOPB
PORT OPB_RNW = OPB_RNW, DIR = IN, BUS = SOPB
PORT OPB_select = OPB_select, DIR = IN, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = IN, BUS = SOPB
PORT OPB_DBus = OPB_DBus, DIR = IN, VEC = [0:C_OPB_DWIDTH-1], BUS = SOPB
PORT Sl_DBus = Sl_DBus, DIR = OUT, VEC = [0:C_OPB_DWIDTH-1], BUS = SOPB
PORT Sl_errAck = Sl_errAck, DIR = OUT, BUS = SOPB
PORT Sl_retry = Sl_retry, DIR = OUT, BUS = SOPB
PORT Sl_toutSup = Sl_toutSup, DIR = OUT, BUS = SOPB
PORT Sl_xferAck = Sl_xferAck, DIR = OUT, BUS = SOPB
## PLB Slave interface
PORT SPLB_Clk = "", DIR = I, SIGIS = Clk, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = Rst, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
## AXI4-Lite Slave interface
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
## XYLON Memory Port for DMA
PORT mclk = "", DIR = I, SIGIS = CLK, BUS = XMB, DESC = "Memory clock for XMB"
PORT mem_req = mem_req, DIR = O, BUS = XMB
PORT mem_wr = mem_wr, DIR = O, BUS = XMB
PORT mem_ack = mem_ack, DIR = I, BUS = XMB
PORT mem_addr = mem_addr, DIR = O, VEC = [31:0], BUS = XMB
PORT mem_data = mem_data_wr, DIR = O, VEC = [C_MEM_DATA_BUS_WIDTH-1:0], BUS = XMB
PORT mem_data_be = mem_data_be, DIR = O, VEC = [C_MEM_DATA_BUS_WIDTH/8-1:0], BUS = XMB
PORT mem_wrack = mem_wrack, DIR = I, BUS = XMB
PORT mem_burst = mem_burst, DIR = O, VEC = [C_MEM_BURST-1:0], BUS = XMB
PORT mem_data_in = mem_data_rd, DIR = I, VEC = [C_MEM_DATA_BUS_WIDTH-1:0], BUS = XMB
PORT mem_data_valid = mem_data_valid, DIR = I, BUS = XMB
## AXI Master Ports
PORT M_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = M_AXI
PORT M_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = M_AXI
PORT M_AXI_AWID = AWID, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT M_AXI_AWADDR = AWADDR, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT M_AXI_AWLEN = AWLEN, DIR = O, VEC = [7:0], BUS = M_AXI
PORT M_AXI_AWSIZE = AWSIZE, DIR = O, VEC = [2:0], BUS = M_AXI
PORT M_AXI_AWBURST = AWBURST, DIR = O, VEC = [1:0], BUS = M_AXI
PORT M_AXI_AWLOCK = AWLOCK, DIR = O, VEC = [1:0], BUS = M_AXI
PORT M_AXI_AWCACHE = AWCACHE, DIR = O, VEC = [3:0], BUS = M_AXI
PORT M_AXI_AWPROT = AWPROT, DIR = O, VEC = [2:0], BUS = M_AXI
PORT M_AXI_AWQOS = AWQOS, DIR = O, VEC = [3:0], BUS = M_AXI
PORT M_AXI_AWVALID = AWVALID, DIR = O, BUS = M_AXI
PORT M_AXI_AWREADY = AWREADY, DIR = I, BUS = M_AXI
PORT M_AXI_WDATA = WDATA, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT M_AXI_WSTRB = WSTRB, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT M_AXI_WLAST = WLAST, DIR = O, BUS = M_AXI
PORT M_AXI_WVALID = WVALID, DIR = O, BUS = M_AXI
PORT M_AXI_WREADY = WREADY, DIR = I, BUS = M_AXI
PORT M_AXI_BID = BID, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT M_AXI_BRESP = BRESP, DIR = I, VEC = [1:0], BUS = M_AXI
PORT M_AXI_BVALID = BVALID, DIR = I, BUS = M_AXI
PORT M_AXI_BREADY = BREADY, DIR = O, BUS = M_AXI
PORT M_AXI_ARID = ARID, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT M_AXI_ARADDR = ARADDR, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT M_AXI_ARLEN = ARLEN, DIR = O, VEC = [7:0], BUS = M_AXI
PORT M_AXI_ARSIZE = ARSIZE, DIR = O, VEC = [2:0], BUS = M_AXI
PORT M_AXI_ARBURST = ARBURST, DIR = O, VEC = [1:0], BUS = M_AXI
PORT M_AXI_ARLOCK = ARLOCK, DIR = O, VEC = [1:0], BUS = M_AXI
PORT M_AXI_ARCACHE = ARCACHE, DIR = O, VEC = [3:0], BUS = M_AXI
PORT M_AXI_ARPROT = ARPROT, DIR = O, VEC = [2:0], BUS = M_AXI
PORT M_AXI_ARQOS = ARQOS, DIR = O, VEC = [3:0], BUS = M_AXI
PORT M_AXI_ARVALID = ARVALID, DIR = O, BUS = M_AXI
PORT M_AXI_ARREADY = ARREADY, DIR = I, BUS = M_AXI
PORT M_AXI_RID = RID, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT M_AXI_RDATA = RDATA, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT M_AXI_RRESP = RRESP, DIR = I, VEC = [1:0], BUS = M_AXI
PORT M_AXI_RLAST = RLAST, DIR = I, BUS = M_AXI
PORT M_AXI_RVALID = RVALID, DIR = I, BUS = M_AXI
PORT M_AXI_RREADY = RREADY, DIR = O, BUS = M_AXI
## SD Card Ports
PORT sd_clk = "", DIR = O, SIGIS = CLK, DESC = "SD Card clock (output)"
PORT sd_dat = "", DIR = IO, ENABLE=MULTI, THREE_STATE=TRUE, VEC = [3:0], PERMIT = BASE_USER, DESC = "SD Card Data (in/out)"
PORT sd_cmd = "", DIR = IO, ENABLE=SINGLE, THREE_STATE=TRUE, PERMIT = BASE_USER, DESC = "SD Card command (in/out)"


## Additional ports
PORT sd_base_rst = "", DIR = O, PERMIT = BASE_USER, DESC = "SD base clock DCM reset (output)"
PORT sd_base_lock = "", DIR = I, PERMIT = BASE_USER, ASSIGNMENT = REQUIRE, DESC = "SD base clock DCM lock (input)"
PORT sd_base_clk = "", DIR = I, SIGIS = CLK, PERMIT = BASE_USER, ASSIGNMENT = REQUIRE, DESC = "SD base clock, should be 100MHz (input)"
PORT sd_int = "", DIR = O, PERMIT = BASE_USER, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, DESC = "SD interrupt (output)"
PORT sd_wp = net_gnd, DIR = I, PERMIT = BASE_USER, DESC = "SD write protect switch (input)"
PORT sd_cd_n = net_gnd, DIR = I, PERMIT = BASE_USER, DESC = "SD card not present (input)"
PORT sd_ci_n = "", DIR = O, PERMIT = BASE_USER, DESC = "SD card not inserted (output)"
PORT sd_led_n = "", DIR = O, PERMIT = BASE_USER, DESC = "LED indicating SD Card is in use (output)"

END

 ----------------------------------------------------------------------------------------------------------------------------------------------------------------

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3 Replies
Highlighted
Anonymous
Not applicable
4,052 Views

Re: EDK XPS error 4207,4208,4209. SD card problem

looks like the tri stated signals are not handled corectly in the MPD file for the Xylon IP. See page 60:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf

 

So port sd_dat for example should look like:

PORT sd_dat = ““, DIR=INOUT, TRI_T=x, TRI_O=y, TRI_T=z, THREE_STATE=TRUE

PORT x = ““, DIR=OUT

PORT y = ““, DIR=OUT

PORT z = ““, DIR=IN

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Teacher
Teacher
4,049 Views
Registered: ‎11-14-2011

Re: EDK XPS error 4207,4208,4209. SD card problem

TRI_T appears twice ...

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Observer
Observer
4,037 Views
Registered: ‎05-14-2013

Re: EDK XPS error 4207,4208,4209. SD card problem

Hello Mr. Shin,

 

XPS instantiates input/output buffers (IO) for these ports and there is no need for you to take care about the internal structure of the buffers (_I, _O and _T signals).

if you declare the ports and connect them to the IP the way it is done in the following lines, it should work fine:

......

PORT logisdhc_0_sd_dat = logisdhc_0_sd_dat, DIR = IO, VEC = [3:0] PORT logisdhc_0_sd_cmd = logisdhc_0_sd_cmd, DIR = IO

.......

BEGIN logisdhc ..... PORT sd_dat = logisdhc_0_sd_dat PORT sd_cmd = logisdhc_0_sd_cmd ...

END

Please note that you are currently using the evaluation license of the IP, which does not include technical support. If you should need further assistance please consider some of the licensing modes which include this feature.

 

Best Regards,

Marko

Xylon Support Team

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