EDK and Spartan-3E Starter kit Rev.D (with XC3S500)

[5201]

When I generate a system with the BSB wizard it will not always pass the memory test. But when I change something it generates sometimes a system that actually run. I think there is a problem with the clock buffers.

I get the warning:

Place:619 - This design either uses more than 8 clock buffers or uses more than 4 DCMs or has clock buffers locked to side-BUFG sites or has DCMs locked to side-DCM sites.

And:

Route:455 - CLK Net:bscan_update may have excessive skew because 2 CLK pins and 0 NON_CLK pins failed to route using a CLK template.

Route:455 - CLK Net:sys_clk_pin_IBUFG may have excessive skew because

      1 CLK pins and 0 NON_CLK pins failed to route using a CLK template.

And more of these.

I use EDK 9.1.02i.

Is there something I can do about this, or is it just due to insufficient resources?

Thanks

[xiaofeip]

Did you check the AR#25390 (http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=25390)?

-xfp

[5201]

Thanks for the reply. I was not aware of the answer record. I have tried it, I put it in the system.ucf file, but with no luck. I looks like that not only the memory controller is not working, because also the hardware debugger fails to connect. I have ordered a new Virtex4 board so I think I throw this board away.

[pbeerak]

Even I had these kinds of problems when I was using the board. As far as I remember, the best way is when you download the Reference design from Xilinx website and when you open it in EDK, do not upgrade the versions of the IP Cores and add the stuff in the UCF from the answer record and that should get you going.

-- parag

[5201]

I am starting to believe that it is a bug what causing me trouble. I have tried to import an old example project. I intended it to use as a starting point for my project, but it forced me to use the new cores. The importer also ended with an error. I don't what to do. I think I leave it this way and wait for the new board. Thanks.