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Visitor al3krab82
Visitor
3,465 Views
Registered: ‎06-03-2009

EDK+ costum IP = Many output; with IO block limitation

Hi all....

I got some prblems in my project, my problem is i have many VHDL output(900 output value), i used costum IP and i saved the output inside the registers(user_logic.vhdl). as we know there is limitation in the FPGA  IO block, i need the Microblaze to access this output and do some process, so please if there is any help.... 

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3 Replies
3,457 Views
Registered: ‎08-21-2008

Re: EDK+ costum IP = Many output; with IO block limitation

Hello.

You can use FIFO (with width+depth accordiing to your data size and number of data) on the VHDL side and you can store the values inside it and then you can access this FIFO from EDK side by giving it necessary signals and reading the values in EDK through microblaze.

Best of luck.
--
Unlimited in my Limits.
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Visitor al3krab82
Visitor
3,451 Views
Registered: ‎06-03-2009

Re: EDK+ costum IP = Many output; with IO block limitation

dear prateek_bhatt ,

 Thanks for ur reply... But realy i dont know how to connect my design to FIFO bec im still new with edk enviroment, so please can u send to me any tutorials regarding FIFO in EDK? THANKS  

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3,444 Views
Registered: ‎08-21-2008

Re: EDK+ costum IP = Many output; with IO block limitation

Hello.

Well that's not a big deal at all. You must be having your design in VHDL in ISE. Do one more thing go to coregen and instantiate a FIFO in your ISE. Then generate the signals according to the timing mentioned in the FIFO's datasheet in order to write data.On one side you write in FIFO in ISE and on the other side you make use of GPIO's to generate read_enable signal in your C code and read data in EDK. Finally map EDK in ISE. I don't have any tutorial regarding this. But once you are clear with the concepts of EDK and FIFO you will definitely be able to do it.

Best of luck.
--
Unlimited in my Limits.
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