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nc6
Participant
Participant
3,796 Views
Registered: ‎05-07-2009

EDK9.1 wierd behaviour of the FPGA after download of download.bit

Hello Group,

 

Tool set:

EDK 9.1i, ISE 9.1i

 

FGPA:

Xilinx Virtex4 XC4VLX100

 

Board:

Custom Board

 

Design IP components:

Microblaze, OPB, opb_user_sl_ip_a, opb_user_sl_ip_b, one DCM, ilmb dlmb(32k)

 

address range of user ips:

opb_user_sl_ip_a 0x40000000- 0x40003FFF

opb_user_sl_ip_b 0x41000000- 0x41003FFF

 

Functionality of user_ips:

slv peripheral a: Blinks 4 leds connected to FPGA using a counter in the c program. I move the 4 bit counter value to the 4 leds using s/w accessible register into the user ip. and that values lights the LEDS. 

 

slv peripheral b: Connects a bunch of FPGA pins to another  bunch of FPGA pins. now the technology of both side of the pins are same. say for example (TTL-TTL). whatever is input using one pin is output to another pin, very straight forward design.

             inside begin of the architecture it looks like

             ADDR1 <= ADDR0;

             wr_en_1 <=wr_en_0;

             ........

             where ADDR1,ADDR0, wr_en_1, wr_en_0 are all external ports of the  slv peripheral b.

 

 

The PROBLEM:

============

 

Case1. when i have only one slave  opb_user_sl_ip_a, in the design and i download the download.bit file there is no problem. the four LEDs blink as a binary counter. This is not a problem.

 

Case2: the problem starts when i add the second slave, opb_user_sl_ip_b. when i add this to the design connect te correct UCF etc. once i download the download.bit file the LEDs wont blink. the impact says program successfully downloaded. i dont change the ucf of the opb_user_sl_ip_a peripheral. I just add the ucf portion of the...user_sl_b peripheral. In the C program i donot do any changes or write anything to the peripheral b, I just write to peripheral a to write the counter data to the s/w accessible registers.

 

 

QUESTIONS:

==========

 

1. Any idea why this wierd behaviour?

2. Is there any other way of connecting two peripheral pins inside the FPGA (technically i dont need to have this ...user_sl_ip_b as a opb peripheral, and i know a way of doing that using ISE nd EDK in tandem) however if anyone in the group have any idea please fill eme in. that will be very helpful.

 

 

thanks for reading. if you have any questions that will help you solve this do post it i will be glad to answer.

 

regards.

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nc6
Participant
Participant
3,795 Views
Registered: ‎05-07-2009

Let me add something to the above.

 

I checked with multimeter during case 1. I get voltage levels at the LED pin.

 

during case 2, i dont get any voltage levels at the LED pins.

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nc6
Participant
Participant
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Registered: ‎05-07-2009

today when i was working in the same project. while trying to "update bitstream" with the elf files it gives

"ERROR:MDT - Data2Mem generated errors during execution"

"make: *** [implementation/download.bit] Error 1" 

 

I am not doing anything different. An area where i have doubt is with the IO data line. I have a IO data bus for which i am using the following in MPD and vhd

 

vhd

 

source_I : in std_logic_vector(0 to n-1);

source_O: out std_logic_vector(0 to n-1); 

source_T : out std_logic_vector(0 to n-1); 

 

 

mpd:

 

PORT source= "", DIR = IO, VEC= [0 to n-1],THREE_STATE = TRUE, ENABLE = MULTI

 

anyone has any idea or suggestions?

Message Edited by nc6 on 07-14-2009 10:18 AM
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