11-07-2012 03:27 AM
I have a zedboard and working with XPS
Is there a way to know the EMIO pin numbers of the IO peripherals of PS when they are assigned to be routed through the PL ??
For example if I have 2 GPIO pin routed through PL how do I know that they are assigned pin number 54 and 55 ( EMIO 0 and EMIO 1) ?
11-07-2012 07:45 AM
11-07-2012 07:52 AM
Thank you for your reply!
But my question is on the tools and where that information is to be found.
It is generic and concerns in general zynq-devices
11-07-2012 08:00 AM
The Zedboard has its own forums, and is its own community.....
My suggestion is to go where the people are reading and responding to such questions, simple or Zynq,
11-07-2012 08:14 AM
Thank you again,
I am aware of the existence of the forum.
What if it was a ZC702 ??? Should I still ask the Zedboard forum?
My question is on the tools!
Does XPS or can i find in a file such as MHS or MSS find info on the alocation
of the EMIO pins? The 7020 zynq provides 118 pins, the tools have to point out what is still available
and were it is mapped.
11-07-2012 08:19 AM
The ZC702 as a Xilinx product,
Is supported by the webcase system (you bought it from us, we answer the question).
You may also post of these forums, and perhaps someone will answer you (for the ZC702, or even the Zed board).
What we did for the Zed board is a bit different (it is both a commercial product one may buy, and it is also a university board that is subsidized).
At this point ALL support for Zed board is intended to be through the Zed board web portal.
11-07-2012 03:07 PM
I do not understand your question. There are 2 GPIO banks which are routed to the EMIOs on the PL side. It is a dedicated 64-bit wide interface. EMIOGPIO[63:0]. If you are using 2 GPIOs, you would control them through a register based on which EMIO you connected to in XPS.
Or are you refering to MIOs which are the fixed PS IOs? MIO[53:0]. There is no MIO 54 or 55.
11-07-2012 11:58 PM
As far as I understand the zynq platform provides the possibility to route I/O peripherals through the PL(programmable logic) and it is called EMIO. Yes it is 64bit wide interface.
My question is:
Is there a way to know to which pins/locations a peripherals is mapped to?
Lets I decide to route 2 GPIO pins through the PL to which EMIO pins are they mapped to?0 and 1 of EMIO?
Is there a way to get this info from somewhere (XPS, mhs, mhh files etc)?
In general how can I know what assignemts the EMIO interface have?
11-08-2012 08:03 AM
Most of the PS IOPs can be routed to either MIO or EMIO (exceptions include USB, SMC, Quad-SPI, SD -- which are only available on MIO). Routing is shown in section 2.5 of TRM v1.3.
GPIOs are a little different. There are 4 banks of GPIOs (32-bit, 22-bit, 32-bit, 32-bit). Banks 0 and 1 route to MIO (54 pins). Banks 2 and 3 route to EMIO (64 sets of signals). Refer to chapter 14 in the TRM.
08-01-2013 01:13 PM
That still does not answer how tools connect EMIO pins to IO output pins.
If i connect 2 GPIOs to EMIO In Vivado you just get bus [1:0], but it does not tell whcih pins/banks inside zynq it is connected too. [63:62] ? Or [1:0] ?
01-26-2015 02:55 PM
I have the same question; I have routed the second ethernet to EMIO, but how do I know which pins the signals are
connected to? I need to know this to design the board; this information doesn't seem to show up in the pinout report;
01-27-2015 07:18 AM
In Linux' GPIO driver numbering, the first EMIO GPIO (i.e. gpio) is numbered just after the first 54 MIO GPIOs. I.e., the MIO GPIOs have reserved numbers 0..53. First EMIO GPIO is thus 54, and last EMIO GPIO is number 117. This numbering is e.g. what you can export in /sys/class/gpio. This does not correspond to any pin numbers, since EMIO has no default pins -- EMIO just leads to your PL, and it is up to you, how you will lead the three signals per GPIO pin (i, o, t for tristate) through.
In my current work, I have used just 2 EMIO GPIOs, numbered in synthesized netlist as [0:1], routed via IOBUFs to custom pins, and I command them using /sys/class/gpio/gpio54 and gpio55.
Hope this helps.
09-26-2015 01:33 PM
I have the exact same question- and I'm NOT uzing the Zedboard. We have our own board and would like to force the CD (card detect) of SD 0 to 0 by connecting that input to an EMIO and then forcing that to 0.
And in the block design editor the tool will cheerfully permit you to connect it to "EMIO". I was hoping then that after building the wrapper might then be sporting some obvious new "SD0_CD" port or some other clue as to how one can actually utilize that "secret EMIO" that somehow gets connected there when on simply configures it to use "EMIO" in the block design. No such luck.
There MUST be a simple answer to this. And I have to believe that the Xilinx people know the answer. But their apparent refusal to tell us means that we'll have to resort to some board rework to get this SD card input tied to ground ;(.
09-26-2015 02:06 PM
Ooops! Sorry- I see it now. When you configure a peripheral port for EMIO then a new port appears in the diagram. So then you can rout this signal anywhere you like in the diagram.
08-08-2016 08:49 AM
I have exact questions you encountered in the past,
I have a ready-design which uses EMIO pins.
That design has a software: In the software, those pins are numbered , 100, 96, 97 etc..
In ready design, some X signal is routed to A16 in Vivado and numbered as 100 in software.
Now I route X signal to N22, doesnt work
I think I have to re-number that pin. What number should I give in software?
#define GPIO_RESET_PIN 100 (When defined as A16)
default_init_param.gpio_resetb = GPIO_RESET_PIN;
08-09-2018 01:44 AM
For the people who still do not have an idea about the mapped pins and mapping pins.
In Vivado block design, you have to enable EMIO.
Once you have done that, it appears in PS7 block in block design window. Set the GPIO port external.
Using navigation flow, Implement the design.
Once the system implemented successfully, open Implemented design.
Then goto window -> I/O Ports window.
In I/O window, you can select, which EMIO should map to which physical pin.
03-26-2019 01:58 PM
Not sure if this thread is still going but I also have been confused. From you I/O Ports you showed where/how the physical port is defined but there is no where it tells you which EMIO bank and pin it is on. After looking at considerable documentation I finally found where it states that BANK 2 is EMIO pins 54- 85 and Bank 3 is EMIO pins 86 - 117, File xgpiops.h makes reference to the banks. So as far as I can tell which EMIO bank and location I assume depends on the bus position you place your I/O on the processing_system7_o GPIO_I(63:0). You would think that a file would be generated with your actual port name to the EMIO pin name.