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Registered: ‎10-21-2012

ERROR:EDK:4075 Design Rule Errors with simple Cores

Hi Forum,

 

   I am using ISE13.2 ML510 Dev board settings.

 

In the EDK I get a strange set of errors when I add a very simple core to the design. The core I created has a very simple counter instantiated in the user_logic.vhd of a new peripheral. When I add the core to the design and then I connect it to the PLB I receive the following errors after clicking a design rule check, I do not know what to make of these:

 

ERROR:EDK:4075 - INSTANCE: DDR2_SDRAM_DIMM0, PORT: SPLB0_Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1023] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v6_04_a\data\mpmc_v2_1_0.mpd line 1013
ERROR:EDK:4075 - INSTANCE: DDR2_SDRAM_DIMM1, PORT: SPLB0_Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1023] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v6_04_a\data\mpmc_v2_1_0.mpd line 1013
ERROR:EDK:4075 - INSTANCE: PCI32_BRIDGE, PORT: Sl_RdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1023] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pci_v1_04_a\data\plbv46_pci_v2_1_0.mpd line 191
ERROR:EDK:4075 - INSTANCE: SysACE_CompactFlash, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1023] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\data\xps_sysace_v2_1_0.mpd line 121
ERROR:EDK:4075 - INSTANCE: mdm_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1023] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 159
ERROR:EDK:4075 - INSTANCE: xps_intc_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1023] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_01_a\data\xps_intc_v2_1_0.mpd line 130
ERROR:EDK:4075 - INSTANCE: blink_test_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1023] - C:\Users\cwilson\Documents\Projects4\OSERDES_v2\pcores\blink_test_v1_00_a\data\blink_test_v2_1_0.mpd line 72

ERROR:EDK:4075 - INSTANCE: data_gen_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1023] - C:\Users\cwilson\Documents\Projects4\OSERDES_v2\pcores\data_gen_v1_00_a\data\data_gen_v2_1_0.mpd line 75

ERROR:EDK:4073 - INSTANCE: mb_plb, PORT: PLB_BE, CONNECTOR: mb_plb_PLB_BE - 16 bit-width connector assigned to 8 bit-width port - C:\Users\cwilson\Documents\Projects4\OSERDES_v2\_xps_tempmhsfilename.mhs line 112

ERROR:EDK:4073 - INSTANCE: mb_plb, PORT: PLB_masterID, CONNECTOR: mb_plb_PLB_masterID - 3 bit-width connector assigned to 2 bit-width port - C:\Users\cwilson\Documents\Projects4\OSERDES_v2\_xps_tempmhsfilename.mhs line 112

ERROR:EDK:4073 - INSTANCE: mb_plb, PORT: PLB_wrDBus, CONNECTOR: mb_plb_PLB_wrDBus - 128 bit-width connector assigned to 64 bit-width port - C:\Users\cwilson\Documents\Projects4\OSERDES_v2\_xps_tempmhsfilename.mhs line 112

 

I created the peripheral with the default setting and really only added my own user ports that go directly from the top level, down to user logic and down into my custom core. I never touched anything with the port for the PLB like the above errors seem to indicate. Has anyone seen these before?

 

Thanks!

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