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bontorhumala
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Registered: ‎01-01-2012

ERROR:NgdBuild:604 in XPS 12.4

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I want to instantiate a netlist core in my custom peripheral (user_logic.vhd). I am using XST 12.4 and ISE 12.4

 

These are my steps:

ISE:

-make ISE project

-use Coregen to make multiplier (mult_pipeline.ngc)

-make a Verilog top-level that instantiate the coregen multiplier:

mult_pipeline mult_pipeline_instc (
    .clk(clk),
    .a(op_a_reg), // Bus [15 : 0]
    .b(op_b_reg), // Bus [15 : 0]
    .p(result_temp)); // Bus [31 : 0]

-save this as mult_core.v

-synthesize the project using XST in ISE, resulting in a .ngc file using ISE (mult_core.ngc)

 

XPS:

-create custom IP template using cip wizard

-make mult_core.v that act as wrapper for the ngc file, add it to \pcores\<my_ip_name>\hdl\verilog\:

 

  module mult_core (
    input [15:0] op_a,
    input [15:0] op_b,
    input valid_inp,
    output reg valid_out,
    output [31:0] result,
    input clk
    );
   endmodule

-edit user_logic.v,  added the following instantiation:

  mult_core  mult_core_instc ( //synthesis attribute box_type mult_core_instc "black_box"
       .op_a(WFIFO2IP_Data[16:31]),
       .op_b(WFIFO2IP_Data[0:15]),
       .valid_inp(slv_reg0),
       .valid_out(slv_reg1),
       .result(IP2RFIFO_Data),
       .clk(Bus2IP_Clk));

-back to XPS, import existing peripheral

-tick use HDL and netlist option as source files

-add mult_core in .pao file

-add mult_core.ngc in insert netlist dialog box

-finished importing IP, add it to XPS project

-connect to PLB bus, generate address

 

Then when I try to generate bitstream, following error occure:

ERROR:NgdBuild:604 - logical block
   'bonti_0/bonti_0/USER_LOGIC_I/mult_core_instc/mult_pipeline_instc' with type
   'mult_pipeline' could not be resolved. A pin name misspelling can cause this,
   a missing edif or ngc file, case mismatch between the block name and the edif
   or ngc file name, or the misspelling of a type name. Symbol 'mult_pipeline'
   is not supported in target 'spartan6'.

This is strange because mult_pipeline_instc is inside mult_core. While I import mult_core.ngc into my custom IP, not mult_pipeline.ngc. Shouldn't the mult_pipeline already implicitly declared as netlist inside mult_core.ngc?

I have read the following support:

http://www.xilinx.com/support/answers/22882.htm

but still the error occurs.

 

Any help is greatly appreciated!

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bontorhumala
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22,611 Views
Registered: ‎01-01-2012
I have solved it, thank you. I recently figured out that instead of adding mult_core.ngc, I should have add mult_pipeline (netlist of the coregen) into the custom peripheral. It works

View solution in original post

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6 Replies
garethc
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17,769 Views
Registered: ‎06-29-2011

Hi bontorhumala,

 

Can you look at AR#:38262 at http://www.xilinx.com/support/answers/38262.htm

 

There are a couple of solutions for this error, can you try and see do they suit with the problem you are having.

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Gareth
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bontorhumala
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22,612 Views
Registered: ‎01-01-2012
I have solved it, thank you. I recently figured out that instead of adding mult_core.ngc, I should have add mult_pipeline (netlist of the coregen) into the custom peripheral. It works

View solution in original post

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9,949 Views
Registered: ‎11-21-2014

Hello, I have exactly the same problem, could you please be more specific to solve this issue, 

thanks in advance, 

 

best regards,

 

gokhankelle


@bontorhumala wrote:
I have solved it, thank you. I recently figured out that instead of adding mult_core.ngc, I should have add mult_pipeline (netlist of the coregen) into the custom peripheral. It works


,

 

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embesys
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Registered: ‎07-24-2015

Hello I am using 14.1 ISE webpack...and I am using Spartan 6 XCSLX9 TGQ144 package...and I got same error..I have seen above link but I am not getting what is box box type and system and I have following lines included in the code...

 

attribute CORE_GENERATION_INFO : string;

 

 

attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";

 

And I am not getting the second solution.... 

 

So please help me

 

Quick response will be always welcome...

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htsvn
Xilinx Employee
Xilinx Employee
7,841 Views
Registered: ‎08-02-2007

hi,

 

can you create a new forum thread as this is already solved?

 

--hs

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aporozh
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Registered: ‎03-03-2014

I have same problem, could you please tell me if you solve your error. Thank you in advance.

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