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Adventurer
Adventurer
998 Views
Registered: ‎01-26-2017

ERROR: [Updatemem 57-153]

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Hi all,

 

I am having a problem programming my MicroBlaze design (specifically, ERROR: [Updatemem 57-153] Failed to update BRAM INIT strings) . I am using a standalone BSP, with my MicroBlaze configured to make use of D & I caches. I have set up the caches in the way suggested in the LMB guide (see below)

 

 

cache.PNG

Here is the memory addresses associated with the IP blocks I am using (see below)

mem_addr.PNG

Then I synth/implement/generate bitstream, generate output products and export to hardware (including bitstream)

 

I'm using one of the example DMA applications that Xilinx provides as my program, so I've got the files setup for that and then I generate the linker script (see below) (note: My I and D Hardware memory maps seem to be fused together? Is this expected?)

gen_linker.PNG

gen_linker_2.PNG

Here is the summary of the linker script (see below)

gen_linker_3.PNG

My question is: It seems that the cache BRAM inits are not being written to correctly, is there something wrong I am doing with my memory addressing? If not that, what is the issue? 

 

I have tried different combinations of ddr4 vs. BRAM but to no avail. 

 

Thanks for your time.

 

 

 

 

--- Estimated Development time: 2*Pi*(planned completion date) ---
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Adventurer
Adventurer
1,178 Views
Registered: ‎01-26-2017

Re: ERROR: [Updatemem 57-153]

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Somewhat amazingly, I went into the linker script and changed everything to BRAM and it worked. I am confused that it worked this time, because I think I tried that before. Still not sure why the D and I caches got fused in the hardware memory map, but I will close the thread now because I guess that is solved....

--- Estimated Development time: 2*Pi*(planned completion date) ---
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Adventurer
Adventurer
1,179 Views
Registered: ‎01-26-2017

Re: ERROR: [Updatemem 57-153]

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Somewhat amazingly, I went into the linker script and changed everything to BRAM and it worked. I am confused that it worked this time, because I think I tried that before. Still not sure why the D and I caches got fused in the hardware memory map, but I will close the thread now because I guess that is solved....

--- Estimated Development time: 2*Pi*(planned completion date) ---
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Moderator
Moderator
956 Views
Registered: ‎09-12-2007

Re: ERROR: [Updatemem 57-153]

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updatemem is for populating the BRAM in the Progammable Logic.

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Adventurer
Adventurer
949 Views
Registered: ‎01-26-2017

Re: ERROR: [Updatemem 57-153]

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right, and I suppose the BRAM that constitutes the MicroBlaze I and D caches are the ones being updated by it. Why would updatemem fail if I was to assign all my memory to be in DDR4 though?
--- Estimated Development time: 2*Pi*(planned completion date) ---
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Moderator
Moderator
940 Views
Registered: ‎09-12-2007

Re: ERROR: [Updatemem 57-153]

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Updatemem would read the location of the data from the ELF. If this does match the address space in the MMI, then it would fail.

if, by chance the address space matched, then the bram location info would fail if this was a DDR

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Adventurer
Adventurer
936 Views
Registered: ‎01-26-2017

Re: ERROR: [Updatemem 57-153]

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@stephenm alright, thanks for the clarification. I appreciate it
--- Estimated Development time: 2*Pi*(planned completion date) ---
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