cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
cerilet
Explorer
Explorer
4,621 Views
Registered: ‎08-26-2014

ERROR: unable to find numeric literal operator 'operator""U' ???

Hi guys,

 

I am working with Zynq and Vivado 2017.4. I had the same code working without any problem, but now it is throwing this error after changing some connections in the block design. I have undone the changes but it still complains.

 

../../MicroZed_design9_bsp/ps7_cortexa9_0/include/xparameters.h:557:40: error: unable to find numeric literal operator 'operator""U'
 #define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 1e+08U

Where is this coming from?

 

Thanks,

 

Cerilet

0 Kudos
Reply
15 Replies
cerilet
Explorer
Explorer
4,571 Views
Registered: ‎08-26-2014

Ok, I have found a temporary solution. I do not know how it happened because is Vivado who generated this line, which is linked to the AXI clock (100MHz).

#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 1e+08U


I have removed the exponent and now it compiles.

#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000U


However, I have no clue why the code compiled before. I have not changed the AXI clock from the previous version to this one.

 

So it is indeed a temporary solution because next time I made any changes in the block design, it will re-generate the xparameters.h file and I will have to modify this line again.

 

Does anyone have an idea where this is coming from?

0 Kudos
Reply
sadanan
Xilinx Employee
Xilinx Employee
4,564 Views
Registered: ‎10-21-2010

Hi,

This is generated by axi_timer driver, based on the HW design.

 

$XILINX_SDK/data/embeddedsw/XilinxProcessorIPLib/drivers/tmrctr_v4_4/data/tmrctr.tcl

 

Can you run the commands listed below in XSCT to see what value you get for CLK_FREQ

1. openhw <path/to/hdf>

2. hsi report_property [lindex [hsi get_pins S_AXI_ACLK [hsi get_cells axi_timer_0]] 0]

0 Kudos
Reply
cerilet
Explorer
Explorer
4,557 Views
Registered: ‎08-26-2014

Hi @sadanan,

 

I just saw in the Vivado Tcl console these warnings:

 

 

WARNING: [IP_Flow 19-3452] Invalid long/float value '1e+08' specified for parameter 'FREQ_HZ(CLK)' for design_9_auto_pc_0.
WARNING: [IP_Flow 19-4684] Expected long value for param s_axi_lite.FREQ_HZ but, float/scientific notation value 1e+08 is provided. The value is converted to long type(100000000)

 

 

And about the commands in the XSCT console, here is the output:

 

Property      Type    Read-only  Value
CLASS         string  true       port
CLK_FREQ      string  true       1e+08
DIRECTION     string  true       I
INTERFACE     bool    true       0
IRQID         string  true       
IS_CONNECTED  bool    true       1
LEFT          string  true       
NAME          string  true       s_axi_aclk
RIGHT         string  true       
SENSITIVITY   enum    true       
TYPE          enum    true       clk

There is still the 1e+08, which is causing the problem.

 

Where is this coming from?

 

0 Kudos
Reply
sadanan
Xilinx Employee
Xilinx Employee
4,540 Views
Registered: ‎10-21-2010

Hi,

I'm not too familiar with Vivado side of things. I guess export2sdk has put the float value into the HDF (that's where XSCT/driver tcl read the frequency). I'm trying to find more details

0 Kudos
Reply
sadanan
Xilinx Employee
Xilinx Employee
4,529 Views
Registered: ‎10-21-2010

Hi @cerilet,

 

export2sdx seems to be picking the frequency from IP XCI file. Can you please check what value you have in the IP configuration wizard and the XCI file?

0 Kudos
Reply
cerilet
Explorer
Explorer
4,517 Views
Registered: ‎08-26-2014

In the IP configuration wizard I have 100 (MHz).

 

Then, in the XCI file I have found this:

 

<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ">1e+08</spirit:configurableElementValue>

So it seems the error comes from here. But why it did not throw an error earlier and now it does? Very weird.

0 Kudos
Reply
cerilet
Explorer
Explorer
4,410 Views
Registered: ‎08-26-2014

Well, I continued working by changing this line on the xparameters.h file every time I modified the block design:

 

#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 1e+08U

by this one:

 

#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000U

 

However, I had to do a major change on the design and I decided to create a new block design from the old one copying all blocks from one design to the new one, and after generating the bitstream and exporing to vivado it does not appears anymore the 1e+8U.

 

Just letting guys from Xilinx know so they might find where this was coming from.

 

Cheers,

 

Cerilet

0 Kudos
Reply
vanmierlo
Mentor
Mentor
4,235 Views
Registered: ‎06-10-2008

Hi,

 

I'm experiencing a similar problem. I also see Vivado generating such warnings and then my device-tree build fails due this 1e+08 value. I'm using Vivado 2017.4 and this just started to happen. Since I did not install anything new in/of Vivado could it come from an OS update? I'm using Ubuntu 16.04.

 

Maarten

0 Kudos
Reply
cerilet
Explorer
Explorer
4,012 Views
Registered: ‎08-26-2014

Hi @vanmierlo,

 

I have no clue where this is coming from. I made some modifications of the block design, and after resynthesizing and generating another bitstream, the error disappeared.

 

Then, I did some other modifications which in my opinion do not have anything directly related to this, and the error appeared again.

 

Very weird. If I ever find out, I will post it here.

 

Best regards,

 

Cerilet

0 Kudos
Reply
vanmierlo
Mentor
Mentor
3,263 Views
Registered: ‎06-10-2008

I had the same experience. It went as easy as it came. I just hope it doesn't resurface any time soon.

0 Kudos
Reply
alexachey
Visitor
Visitor
3,113 Views
Registered: ‎07-25-2018

I'm having a very similar problem as well.   I had a design that was working properly with Vivado 2017.4.1 under Windows 7 and the SDK/Petalinux in a VM.   I then created and inserted a new IP package with an AXI-Lite + and AXIStream interface into the diagram and tried building with just the created "template".   After that I started getting warnings like the below:

 

WARNING: [IP_Flow 19-3452] Invalid long/float value '1e+08' specified for parameter 'FREQ_HZ(CLK)' for Z_design_auto_pc_0.

WARNING: [IP_Flow 19-4684] Expected long value for param ACLK.FREQ_HZ but, float/scientific notation value 1e+08 is provided. The value is converted to long type(100000000)

 

 

I can ignore the warnings, but the device tree build fails when it gets to my axi_uart16550 with

FATAL ERROR: Unable to parse input tree

 

If I look at the line it fails on, it's the frequency: 

axi_uart16550_2: serial@43c00000 {
  clock-frequency = <1e+08>;     <--fails here
  clock-names = "ref_clk";

 

In my case there's no "U" causing trouble though.

 

Removing the IP from the block diagram doesn't fix things.   

 

 

0 Kudos
Reply
cerilet
Explorer
Explorer
3,094 Views
Registered: ‎08-26-2014

Try changing the 1e+08 by 100000000. It worked for me.

Cheers.

Cerilet
0 Kudos
Reply
vanmierlo
Mentor
Mentor
3,087 Views
Registered: ‎06-10-2008

Manually? Every time you rebuild your petalinux? That's not a comfortable way to work.

0 Kudos
Reply
cerilet
Explorer
Explorer
3,074 Views
Registered: ‎08-26-2014

Well, it happened to me from time to time. But yes, I couldn't find the source of the error so I did it manually. That's something the guys from @xilinx should find and repair.

Try to generate again the whole Bitstream. As I said, this error appears only from time to time.

Good luck.

Cerilet
0 Kudos
Reply
sanjivgarg
Adventurer
Adventurer
2,193 Views
Registered: ‎12-10-2014

All of a sudden I started getting this error also for  2018.1. It's a pain to have to fixed it manually all the  time.

0 Kudos
Reply