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Registered: ‎01-16-2008

Edk dcm constraints

Hello everybody.

I have an algorithm running in post place & route simulation properly and it is not working on the virtex II pro i am download it.

The flow of edk(netlist,bitsream) is produced without any errors.i am wondering why?

I have put a dcm component with coregen into my design to fall down the frequency.So i have two clocks the clk that is connected to the OPB clk and is at 100MHz and the 90Mhz that the algorithm runs output of dcm.(this because i my design has maximum frequency 94 which is not enough for the opb clk, i loose data ).I can see a warning about timing constraint which is not met of the dcm the project creates for multiplying the processor frequency.


Any ideas?


Thanks a lot!   

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