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quinchi16
Visitor
Visitor
5,335 Views
Registered: ‎08-13-2008

Error: MDT

Hi,

 

I'm adding a IP to my PPC, but when I generate the bitstream appear the following :

 

ERROR:MDT - Sl_rdDBus (momo_0_wrapper) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 44 - VEC
   evaluation of (C_PLB_DWIDTH-1) failed!
ERROR:MDT - PLB_ABus (momo_0_wrapper) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 53 - VEC
   evaluation of (C_PLB_AWIDTH-1) failed!
ERROR:MDT - PLB_BE (momo_0_wrapper) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 54 - VEC
   evaluation of ((C_PLB_DWIDTH/8)-1) failed!
ERROR:MDT - PLB_masterID (momo_0_wrapper) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 59 - VEC
   evaluation of (C_PLB_MID_WIDTH-1) failed!
ERROR:MDT - PLB_wrDBus (momo_0_wrapper) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 73 - VEC
   evaluation of (C_PLB_DWIDTH-1) failed!
ERROR:MDT - Sl_rdDBus (momo_0) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 44 - VEC
   evaluation of (C_PLB_DWIDTH-1) failed!
ERROR:MDT - PLB_ABus (momo_0) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 53 - VEC
   evaluation of (C_PLB_AWIDTH-1) failed!
ERROR:MDT - PLB_BE (momo_0) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 54 - VEC
   evaluation of ((C_PLB_DWIDTH/8)-1) failed!
ERROR:MDT - PLB_masterID (momo_0) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 59 - VEC
   evaluation of (C_PLB_MID_WIDTH-1) failed!
ERROR:MDT - PLB_wrDBus (momo_0) -
   C:\workspace\memo\pcores\momo_v1_00_a\data\momo_v2_1_0.mpd line 73 - VEC
   evaluation of (C_PLB_DWIDTH-1) failed!
 

 I check this in the help, but the page has problems.

Anyone can help me?

thanks. 

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htsvn
Xilinx Employee
Xilinx Employee
5,324 Views
Registered: ‎08-02-2007

Hello,

 

It seems that this is a custom core.

 

Check the parameter mentioned in the error. If you need an example of a MPD you can look for one in EDK installation.

 

Regards

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quinchi16
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5,298 Views
Registered: ‎08-13-2008

Hi,

 

Yes, I want to add a custom core (my own dual port memory or is there another solution? a memory dual port to PPC).

I import my peripheral, changing the user_logic 

 

user_logic.vhd 

 

 

memory_1 : memory_core
  generic map(
        width => width,
        depth => depth,
        addr =>addr
        )
    port map(
          Clk => Bus2IP_Clk,
           Enable => Enable,
            Re => Re,
           Wr => Wr,
           Read_Addr => Read_Addr,
           Write_Addr => Write_Addr,
           Data_in => Data_in,
           Data_out => Data_o    
    );

  -- implement slave model register(s)
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
          enable <= '0';
          Re <=    '0';
          estado_R <= inicio;
      else
          if(Bus2IP_WrCE(0) = '1') then
             enable <= '1';
              Re <=    '1';
              estado_R <= inicio;
              Read_Addr <= Bus2IP_Data(0 to addr-1);
          end if;
          case estado_R is
                when inicio =>
                    if (enable = '1') then
                        estado_R <= espera;
                         
                        -- rd_ram = '0'
               end if;         
                when espera =>
               if(Bus2IP_RdCE(0) = '1') then
                      IP2Bus_Data (0 to width-1) <= Data_o;-- slv_ip2bus_data(0 to width-1) <= Data_o;
                     -- Bus2IP_Data <= Data_o;
                       estado_R <= leido;
                    end if;  
                when leido =>   
                   enable <= '0';
                   Re <=    '0';
                    estado_R <= inicio;
            end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

end IMP;

 

I check the parameter mentioned, but I don't find the problem. 

I have changed many times the user_logic, but  I continue having the same error.

 

 

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Chadn_na
Xilinx Employee
Xilinx Employee
5,293 Views
Registered: ‎08-15-2007

It looks like it is an issue with your MPD file, can you post your MPD file here.
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quinchi16
Visitor
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5,276 Views
Registered: ‎08-13-2008

Hi,

 

Post the errors and the MPD.

Thanks 

 

 

ERROR:MDT - Sl_DBus (nuevam_0_wrapper) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 35 - VEC
   evaluation of (C_OPB_DWIDTH-1) failed!
ERROR:MDT - OPB_ABus (nuevam_0_wrapper) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 40 - VEC
   evaluation of (C_OPB_AWIDTH-1) failed!
ERROR:MDT - OPB_BE (nuevam_0_wrapper) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 41 - VEC
   evaluation of ((C_OPB_DWIDTH/8)-1) failed!
ERROR:MDT - OPB_DBus (nuevam_0_wrapper) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 42 - VEC
   evaluation of (C_OPB_DWIDTH-1) failed!

ERROR:MDT - Sl_DBus (nuevam_0) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 35 - VEC
   evaluation of (C_OPB_DWIDTH-1) failed!
ERROR:MDT - OPB_ABus (nuevam_0) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 40 - VEC
   evaluation of (C_OPB_AWIDTH-1) failed!
ERROR:MDT - OPB_BE (nuevam_0) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 41 - VEC
   evaluation of ((C_OPB_DWIDTH/8)-1) failed!
ERROR:MDT - OPB_DBus (nuevam_0) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 42 - VEC
   evaluation of (C_OPB_DWIDTH-1) failed!
ERROR:MDT - Sl_DBus (nuevam_0) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 35 - VEC
   evaluation of (C_OPB_DWIDTH-1) failed!
ERROR:MDT - OPB_ABus (nuevam_0) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 40 - VEC
   evaluation of (C_OPB_AWIDTH-1) failed!
ERROR:MDT - OPB_BE (nuevam_0) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 41 - VEC
   evaluation of ((C_OPB_DWIDTH/8)-1) failed!
ERROR:MDT - OPB_DBus (nuevam_0) -
   C:\workspace\nuevo\pcores\nuevam_v1_00_a\data\nuevam_v2_1_0.mpd line 42 - VEC
   evaluation of (C_OPB_DWIDTH-1) failed!
Completion time: 2.00 seconds
ERROR:MDT - platgen failed with errors!

MPD

 

 

BEGIN nuevam

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = NUEVAM


## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB

## Generics for VHDL or Parameters for Verilog
PARAMETER width = 4, DT = INTEGER
PARAMETER depth = 4, DT = INTEGER
PARAMETER addr = 2, DT = INTEGER
PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x100
PARAMETER C_HIGHADDR = 0x0000ffff, DT = std_logic_vector, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB, ASSIGNMENT = CONSTANT
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB, RANGE = (8, 16, 32)
PARAMETER C_FAMILY = virtex2p, DT = STRING

## Ports
PORT OPB_Clk = "", DIR = I, SIGIS = Clk, BUS = SOPB
PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = Rst, BUS = SOPB
PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB
PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB
PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = SOPB
PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = SOPB
PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = SOPB
PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB

END
 

 

 

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