06-02-2020 06:00 AM
I should support my colleague in an existing Virtex5 project with Platform Studio 14.7.
Netlist generation will work done. But if I start implementation I will get this error:
Checking expanded design ... ERROR:NgdBuild:604 - logical block 'xps_ll_temac_Cu/xps_ll_temac_Cu/I_TX0/I_TX_CSUM_FIFO/V5_AND_EARLIER.I_SYNC_F IFO_BRAM' with type 'system_xps_ll_temac_cu_wrapper_fifo_generator_v4_3_1' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'system_xps_ll_temac_cu_wrapper_fifo_generator_v4_3_1' is not supported in target 'virtex5'.
Do you know where the problem is? What can I do, that I can implement our design?
Thank you for your help.