cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
someoneharsha
Visitor
Visitor
2,373 Views
Registered: ‎11-09-2011

Error in EDK (Digilent atlys board)

HI,

 

I am using a bootloader to copy the image from SPI_FLASH to external memory (DDR2). I used XPS_MCH_EMC controller to drive the SPI_FLASH and MPMC to DDR2. But during generation of bitstream in EDK there is an error after mapping is done. I have attached MHS file and also UCF file .Error as follows

 

ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design
cannot be automatically placed.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1

 

 

---------MHS FILE-------------


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.2 Build EDK_O.61xd
# Tue Jan 31 20:55:22 2012
# Target Board: Digilent Atlys Rev C
# Family: spartan6
# Device: xc6slx45
# Package: csg324
# Speed Grade: -2
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 66.7
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
PARAMETER VERSION = 2.1.0


PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
PORT fpga_0_MCB_DDR2_mcbx_dram_addr_pin = fpga_0_MCB_DDR2_mcbx_dram_addr_pin, DIR = O, VEC = [12:0]
PORT fpga_0_MCB_DDR2_mcbx_dram_ba_pin = fpga_0_MCB_DDR2_mcbx_dram_ba_pin, DIR = O, VEC = [2:0]
PORT fpga_0_MCB_DDR2_mcbx_dram_ras_n_pin = fpga_0_MCB_DDR2_mcbx_dram_ras_n_pin, DIR = O
PORT fpga_0_MCB_DDR2_mcbx_dram_cas_n_pin = fpga_0_MCB_DDR2_mcbx_dram_cas_n_pin, DIR = O
PORT fpga_0_MCB_DDR2_mcbx_dram_we_n_pin = fpga_0_MCB_DDR2_mcbx_dram_we_n_pin, DIR = O
PORT fpga_0_MCB_DDR2_mcbx_dram_cke_pin = fpga_0_MCB_DDR2_mcbx_dram_cke_pin, DIR = O
PORT fpga_0_MCB_DDR2_mcbx_dram_clk_pin = fpga_0_MCB_DDR2_mcbx_dram_clk_pin, DIR = O
PORT fpga_0_MCB_DDR2_mcbx_dram_clk_n_pin = fpga_0_MCB_DDR2_mcbx_dram_clk_n_pin, DIR = O
PORT fpga_0_MCB_DDR2_mcbx_dram_dq_pin = fpga_0_MCB_DDR2_mcbx_dram_dq_pin, DIR = IO, VEC = [15:0]
PORT fpga_0_MCB_DDR2_mcbx_dram_dqs_pin = fpga_0_MCB_DDR2_mcbx_dram_dqs_pin, DIR = IO
PORT fpga_0_MCB_DDR2_mcbx_dram_dqs_n_pin = fpga_0_MCB_DDR2_mcbx_dram_dqs_n_pin, DIR = IO
PORT fpga_0_MCB_DDR2_mcbx_dram_udqs_pin = fpga_0_MCB_DDR2_mcbx_dram_udqs_pin, DIR = IO
PORT fpga_0_MCB_DDR2_mcbx_dram_udqs_n_pin = fpga_0_MCB_DDR2_mcbx_dram_udqs_n_pin, DIR = IO
PORT fpga_0_MCB_DDR2_mcbx_dram_udm_pin = fpga_0_MCB_DDR2_mcbx_dram_udm_pin, DIR = O
PORT fpga_0_MCB_DDR2_mcbx_dram_ldm_pin = fpga_0_MCB_DDR2_mcbx_dram_ldm_pin, DIR = O
PORT fpga_0_MCB_DDR2_mcbx_dram_odt_pin = fpga_0_MCB_DDR2_mcbx_dram_odt_pin, DIR = O
PORT fpga_0_MCB_DDR2_rzq_pin = fpga_0_MCB_DDR2_rzq_pin, DIR = IO
PORT fpga_0_MCB_DDR2_zio_pin = fpga_0_MCB_DDR2_zio_pin, DIR = IO
PORT fpga_0_SPI_FLASH_SCK_pin = fpga_0_SPI_FLASH_SCK_pin, DIR = IO
PORT fpga_0_SPI_FLASH_MISO_pin = fpga_0_SPI_FLASH_MISO_pin, DIR = IO
PORT fpga_0_SPI_FLASH_MOSI_pin = fpga_0_SPI_FLASH_MOSI_pin, DIR = IO
PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
PORT SPI_FLASH_SPISEL_pin = net_vcc, DIR = I
PORT SPI_FLASH_SS_pin = SPI_FLASH_SS, DIR = IO
PORT xps_mch_emc_0_Mem_A_pin = xps_mch_emc_0_Mem_A, DIR = O, VEC = [0:31]
PORT xps_mch_emc_0_Mem_RPN_pin = xps_mch_emc_0_Mem_RPN, DIR = O
PORT xps_mch_emc_0_Mem_CEN_pin = xps_mch_emc_0_Mem_CEN, DIR = O
PORT xps_mch_emc_0_Mem_OEN_pin = xps_mch_emc_0_Mem_OEN, DIR = O
PORT xps_mch_emc_0_Mem_WEN_pin = xps_mch_emc_0_Mem_WEN, DIR = O
PORT xps_mch_emc_0_Mem_BEN_pin = xps_mch_emc_0_Mem_BEN, DIR = O, VEC = [0:3]
PORT xps_mch_emc_0_Mem_CE_pin = xps_mch_emc_0_Mem_CE, DIR = O
PORT xps_mch_emc_0_Mem_ADV_LDN_pin = xps_mch_emc_0_Mem_ADV_LDN, DIR = O
PORT xps_mch_emc_0_Mem_CKEN_pin = xps_mch_emc_0_Mem_CKEN, DIR = O
PORT xps_mch_emc_0_Mem_DQ_pin = xps_mch_emc_0_Mem_DQ, DIR = IO, VEC = [0:31]


BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_USE_BARREL = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER HW_VER = 8.20.a
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
PORT MB_RESET = mb_reset
END

BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = clk_66_6667MHzPLL0
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clk_66_6667MHzPLL0
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clk_66_6667MHzPLL0
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER HW_VER = 1.02.a
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_Uart_1_RX_pin
PORT TX = fpga_0_RS232_Uart_1_TX_pin
END

BEGIN mpmc
PARAMETER INSTANCE = MCB_DDR2
PARAMETER C_NUM_PORTS = 1
PARAMETER C_PORT_CONFIG = 1
PARAMETER C_MCB_LOC = MEMC3
PARAMETER C_MEM_CALIBRATION_SOFT_IP = TRUE
PARAMETER C_MEM_SKIP_IN_TERM_CAL = 0
PARAMETER C_MEM_SKIP_DYNAMIC_CAL = 0
PARAMETER C_MCB_RZQ_LOC = L6
PARAMETER C_MCB_ZIO_LOC = C2
PARAMETER C_MEM_PARTNO = MT47H64M16XX-25E
PARAMETER C_MEM_ODT_TYPE = 3
PARAMETER C_MEM_DATA_WIDTH = 16
PARAMETER C_DDR2_DQSN_ENABLE = 1
PARAMETER C_PIM0_BASETYPE = 2
PARAMETER HW_VER = 6.04.a
PARAMETER C_MPMC_BASEADDR = 0x88000000
PARAMETER C_MPMC_HIGHADDR = 0x8fffffff
BUS_INTERFACE SPLB0 = mb_plb
PORT MPMC_Clk0 = clk_66_6667MHzPLL0
PORT MPMC_Rst = sys_periph_reset
PORT MPMC_Clk_Mem_2x = clk_600_0000MHzPLL0_nobuf
PORT MPMC_Clk_Mem_2x_180 = clk_600_0000MHz180PLL0_nobuf
PORT MPMC_PLL_Lock = Dcm_all_locked
PORT mcbx_dram_addr = fpga_0_MCB_DDR2_mcbx_dram_addr_pin
PORT mcbx_dram_ba = fpga_0_MCB_DDR2_mcbx_dram_ba_pin
PORT mcbx_dram_ras_n = fpga_0_MCB_DDR2_mcbx_dram_ras_n_pin
PORT mcbx_dram_cas_n = fpga_0_MCB_DDR2_mcbx_dram_cas_n_pin
PORT mcbx_dram_we_n = fpga_0_MCB_DDR2_mcbx_dram_we_n_pin
PORT mcbx_dram_cke = fpga_0_MCB_DDR2_mcbx_dram_cke_pin
PORT mcbx_dram_clk = fpga_0_MCB_DDR2_mcbx_dram_clk_pin
PORT mcbx_dram_clk_n = fpga_0_MCB_DDR2_mcbx_dram_clk_n_pin
PORT mcbx_dram_dq = fpga_0_MCB_DDR2_mcbx_dram_dq_pin
PORT mcbx_dram_dqs = fpga_0_MCB_DDR2_mcbx_dram_dqs_pin
PORT mcbx_dram_dqs_n = fpga_0_MCB_DDR2_mcbx_dram_dqs_n_pin
PORT mcbx_dram_udqs = fpga_0_MCB_DDR2_mcbx_dram_udqs_pin
PORT mcbx_dram_udqs_n = fpga_0_MCB_DDR2_mcbx_dram_udqs_n_pin
PORT mcbx_dram_udm = fpga_0_MCB_DDR2_mcbx_dram_udm_pin
PORT mcbx_dram_ldm = fpga_0_MCB_DDR2_mcbx_dram_ldm_pin
PORT mcbx_dram_odt = fpga_0_MCB_DDR2_mcbx_dram_odt_pin
PORT rzq = fpga_0_MCB_DDR2_rzq_pin
PORT zio = fpga_0_MCB_DDR2_zio_pin
END

BEGIN xps_spi
PARAMETER INSTANCE = SPI_FLASH
PARAMETER C_FIFO_EXIST = 0
PARAMETER C_SCK_RATIO = 128
PARAMETER C_NUM_SS_BITS = 1
PARAMETER C_NUM_TRANSFER_BITS = 8
PARAMETER HW_VER = 2.02.a
PARAMETER C_BASEADDR = 0x83400000
PARAMETER C_HIGHADDR = 0x8340ffff
BUS_INTERFACE SPLB = mb_plb
PORT SPISEL = net_vcc
PORT SCK = fpga_0_SPI_FLASH_SCK_pin
PORT MISO = fpga_0_SPI_FLASH_MISO_pin
PORT MOSI = fpga_0_SPI_FLASH_MOSI_pin
PORT SS = SPI_FLASH_SS
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 600000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = PLL0
PARAMETER C_CLKOUT0_BUF = FALSE
PARAMETER C_CLKOUT1_FREQ = 600000000
PARAMETER C_CLKOUT1_PHASE = 180
PARAMETER C_CLKOUT1_GROUP = PLL0
PARAMETER C_CLKOUT1_BUF = FALSE
PARAMETER C_CLKOUT2_FREQ = 66666666
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = PLL0
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 4.02.a
PORT CLKIN = CLK_S
PORT CLKOUT0 = clk_600_0000MHzPLL0_nobuf
PORT CLKOUT1 = clk_600_0000MHz180PLL0_nobuf
PORT CLKOUT2 = clk_66_6667MHzPLL0
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER HW_VER = 2.00.b
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 3.00.a
PORT Slowest_sync_clk = clk_66_6667MHzPLL0
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_mch_emc
PARAMETER INSTANCE = xps_mch_emc_0
PARAMETER HW_VER = 3.01.a
PARAMETER C_MEM0_BASEADDR = 0x86210000
PARAMETER C_MEM0_HIGHADDR = 0x8621ffff
BUS_INTERFACE SPLB = mb_plb
PORT Mem_A = xps_mch_emc_0_Mem_A
PORT Mem_RPN = xps_mch_emc_0_Mem_RPN
PORT Mem_CEN = xps_mch_emc_0_Mem_CEN
PORT Mem_OEN = xps_mch_emc_0_Mem_OEN
PORT Mem_WEN = xps_mch_emc_0_Mem_WEN
PORT Mem_BEN = xps_mch_emc_0_Mem_BEN
PORT Mem_CE = xps_mch_emc_0_Mem_CE
PORT Mem_ADV_LDN = xps_mch_emc_0_Mem_ADV_LDN
PORT Mem_CKEN = xps_mch_emc_0_Mem_CKEN
PORT Mem_DQ = xps_mch_emc_0_Mem_DQ
PORT RdClk = CLK_S
END

 

ANY SUGESTIONS ACCEPTED.

0 Kudos
1 Reply
austin
Scholar
Scholar
2,370 Views
Registered: ‎02-27-2008

s,

And you would like us to debug this, and show you were you made the mistake?

Perhaps you could look at the error messages, and find your mistakes, yourself?

What did you change that led to the error messages appearing?

Best plan is to start with something that works, and then add what you need, item by item, checking it after each step.
Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos