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Registered: ‎10-30-2020

Error when trying to make an application project in SDK

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Hello. I am working on a project where I am developing an AXI IP core that will be used to decode a PWM signal. The output register will contain data about period and duty-cycle of the signal.

The IP has been coded in VHDL and the code has been tested by itself on a Basys3 evaluation board before it was packaged as an AXI4 IP.

After having created ti AXI4 IP, I wanted to test it on said Basys3 board, using a Microblaze in a Block design. I inserted the Microblaze, my own IP and a GPIO module and ran the block and connection automation.

AndreasBMadsen_0-1604057278959.png

As a clock source I have used the signal "clk" from my constraint file, which is a 100 MHz clock source.

The output of the GPIO connects to "led", which is a series of 16 LEDs on the Basys3 board.

The JC port in the block design is a pmod header on the board and btnC is connected to a tactile switch.

To try to avoid ports that are unconnected, I have also connected the external reset signal and extern interrupt signals to switches on the board.

I have created a HDL wrapper and I am able to generate a bitstream and export the hardware without a problem. However, when I open the SDK environment and try to create a project, based on the exported hardware, I get the following error:

(XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_ucos_cpu_microblaze_v1_43::generate : could not read "C:/Xilinx/SDK/2018.3/gnu/microblaze/nt/microblaze-xilinx-elf/lib/bs/m/le/libgloss.a": no such file or directory
while executing

Here is the full view of the SDK log.

AndreasBMadsen_1-1604057467471.png

I have used Windows File Explorer to look for the specific file that is mentioned, and the subfolder

C:/Xilinx/SDK/2018.3/gnu/microblaze/nt/microblaze-xilinx-elf/lib/bs/m/le

does not exist, which of course explains this message, but I don't know why it is so.

I have been trying to find out what is wrong, but cannot find any answers. Could it be that something has gone wrong during my installation of Vivado 2018.3?

I am quite new to VHDL and Vivado, so the problem could also be located somewhere else in my project (I can upload project files if necessary), but the VHDL code has been synthesized and tested on the Basys3 kit with no problems.

Does anyone know this problem and how to fix it?

Thanks in advance

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Adventurer
Adventurer
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Registered: ‎03-13-2019

Hello @AndreasBMadsen 

Currently are you getting any critical warning in vivado if not 
Can you try these 2 methods.

Method 1: 
In your block design please look at Microblaze debug module. The interrupt output is disconnected.
Please connect it to concat block and connect it to interrupt controller.
Later generate bit stream and check it.
It may resolve your error.

Method 2: 
As you are mentioning there may be installation problems, you can download the Xilinx Git repositories here
https://github.com/Xilinx/embeddedsw

Go to SDK and hit Xilinx->repository-> 

Add the downloaded repository path in the first section and build the project.
ex: .../embeddedsw/XilinxProcessorIPLib/drivers path

Hope this helps

If these two methods did not solve the issue then HDF file has to be checked.

Regards
Pavan
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Registered: ‎05-08-2012

Hi @AndreasBMadsen 

Does this project use Petalinux? If so, this might be better suited on the Embedded Linux board. I see several forums posts and an answer record with the same error ID relating to Petalinux such as the following:

 

https://www.xilinx.com/support/answers/65048.html

https://forums.xilinx.com/t5/Embedded-Linux/ERROR-Hsi-55-1545-Problem-running-tcl-command-sw-cpu-cortexa53/m-p/943966

 

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Registered: ‎10-30-2020

No, unfortunately not. I am trying to create a standalone project, not based om any operating system.

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Registered: ‎10-30-2020

By the way, it is probably worth mentioning that I have also tried doing the same thing where I have not added my own IP - only a GPIO module for testing. This does not work either. I have also tested this on another computer. Furthermore, I am using Vivado 2018.3

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Registered: ‎05-08-2012

Hi @AndreasBMadsen 

Is the HDF available to upload for the community to help further?

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I have just tried, but each time I try to upload it, I receive the following error message:

AndreasBMadsen_1-1604392369373.png

I don't know what the cause of this problem is

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Registered: ‎03-13-2019

Hello @AndreasBMadsen 

Currently are you getting any critical warning in vivado if not 
Can you try these 2 methods.

Method 1: 
In your block design please look at Microblaze debug module. The interrupt output is disconnected.
Please connect it to concat block and connect it to interrupt controller.
Later generate bit stream and check it.
It may resolve your error.

Method 2: 
As you are mentioning there may be installation problems, you can download the Xilinx Git repositories here
https://github.com/Xilinx/embeddedsw

Go to SDK and hit Xilinx->repository-> 

Add the downloaded repository path in the first section and build the project.
ex: .../embeddedsw/XilinxProcessorIPLib/drivers path

Hope this helps

If these two methods did not solve the issue then HDF file has to be checked.

Regards
Pavan
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Registered: ‎10-30-2020

Yes, I am getting 30 critical warnings in Vivado:

AndreasBMadsen_0-1604400079366.png

They are all related to my constraint files - the one used in the current project and th OOC constraint file I have used when packaging the IP core. Unfortunately, I get the same error as previously when trying to upload these files in here, but their contents are respectively:

Basys3_Master.xdc

 

# This file is a general .xdc for the Basys3 rev B board
# To use it in a project:
# - uncomment the lines corresponding to used pins
# - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
#library IEEE;
#use IEEE.STD_LOGIC_1164.ALL;
#use IEEE.STD_LOGIC_ARITH.ALL;
#use IEEE.STD_LOGIC_UNSIGNED.ALL;

# Clock signal
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

# Switches
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {sw[0]}]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]

# LEDs
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]
set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]
set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]
set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]
set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]
set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]
set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]
set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]
set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]
set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]
set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]
set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]
set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]
set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]


#7 segment display
set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { seg[0] }]
set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { seg[1] }]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { seg[2] }]
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { seg[3] }]
set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { seg[4] }]
set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { seg[5] }]
set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { seg[6] }]

set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports dp]

set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]
set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]
set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]
set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]


#Buttons
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]

# Dette er nødvendigt hvis man ønsker at bruge disse signaler
## som et Clock signal
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btnC_IBUF]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btnU_IBUF]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btnL_IBUF]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btnR_IBUF]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btnD_IBUF]

##Pmod Header JA
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}] #Sch name = JA1
#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}] #Sch name = JA2
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}] #Sch name = JA3
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}] #Sch name = JA4
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}] #Sch name = JA7
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}] #Sch name = JA8
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}] #Sch name = JA9
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}] #Sch name = JA10

##Pmod Header JB
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}] #Sch name = JB1
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}] #Sch name = JB2
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}] #Sch name = JB3
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}] #Sch name = JB4
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}] #Sch name = JB7
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}] #Sch name = JB8
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}] #Sch name = JB9
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}] #Sch name = JB10

##Pmod Header JC
#Sch name = JC1
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}]
#Sch name = JC2
set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}]
#Sch name = JC3
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}]
#Sch name = JC4
set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}]
#Sch name = JC7
set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}]
#Sch name = JC8
set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}]
#Sch name = JC9
set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}]
#Sch name = JC10
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}]

##Pmod Header JXADC

#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { vauxp6 }]; #Sch name = XA1_P & Vauxp6
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports { vauxp14 }]; #Sch name = XA2_P & Vauxp14
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports { vauxp7 }]; #Sch name = XA3_P & Vauxp7
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports { vauxp15 }]; #Sch name = XA4_P & Vauxp15
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports { vauxn6 }]; #Sch name = XA1_N & Vauxn6
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { vauxn14 }]; #Sch name = XA2_N & Vauxn14
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports { vauxn7 }]; #Sch name = XA3_N & Vauxn7
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports { vauxn15 }]; #Sch name = XA4_N & Vauxn15


##VGA Connector
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]

#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync]
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync]


##USB-RS232 Interface
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx]
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx]


##USB HID (PS/2)
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
# set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
# set_property PULLUP true [get_ports PS2Clk]
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
# set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
# set_property PULLUP true [get_ports PS2Data]


##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]

 

PWM_decoder_ooc.xdc.xdc

# Clock signal
create_clock -period 10.00 [get_ports clk]

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Registered: ‎03-13-2019

Hello @AndreasBMadsen 

I think constraints are not causing the mentioned error in SDK.

It looks like ok.

Can you try method 1 which I mentioned?

Regards
Pavan

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Registered: ‎10-30-2020

I have just tried it, and unfortunately I still receive the same error :(. I will try method 2 then

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Registered: ‎10-30-2020

Finally :D! I tried out your second suggestion and it looks like it is working. Now the Vivado SDK allows me to create a project without any errors. I have tried following a Microblaze tutorial and I still cannot get this to work, but it is probably just some other error.

Why is it that these files I downloaded from Git solves my issue?

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Registered: ‎03-13-2019

Hello 

Glad to hear it is working

Why is it that these files I downloaded from Git solves my issue?
>> The files you have downloaded is nothing but Xilinx driver files which will be already present in your SDK installation directory.

For some reason (I am not sure if it is bug or error in installation) these files cannot be fetched during the application project creation.

Regards
pavan

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Still, I am very confused by why this happens. I have tried re-installing Vivado 2018.3 three times, and the problem still persists.

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