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Newbie zluo
Newbie
1,848 Views
Registered: ‎02-01-2013

FIQ can not be disable on ZYNQ 7000 EPP - ZC702 board

mrs r0, cpsr

bic r0, r0, #MASK_MODE

orr r0, r0, #MODE_SYS | PSR_I_BIT | PSR_F_BIT

msr cpsr, r0

After the above instruction executed, the FIQ still not be masked.

The SCR is 0 before the instruction execute.

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Visitor sandro17
Visitor
823 Views
Registered: ‎02-06-2016

Re: FIQ can not be disable on ZYNQ 7000 EPP - ZC702 board

Accordingly to the ARMv7 specification (ARMv7 reference manual) ARMv7 implementations can be configured so that the CPSR.F bit cannot be set to 1 by an MSR or CPS instruction. 

 

This is defined as Non-maskable FIQ (NMFI) operation, and you can find it in the SCTLR.NMFI bit (read-only bit).

 

 

Since it is IMPLEMENTATION DEFINED whether an ARMv7 processor supports NMFIs, in the case of ZYNQ Xilinx decided to set this bit. This means software cannot set the CPSR.F bit to 1, i.e. software cannot mask FIQs.

 

The only way to set CPSR.F is by FIQ and Monitor exception entries...

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