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Visitor sssingh
Visitor
14,771 Views
Registered: ‎04-27-2008

FSL and bus vs ports

When I instantiate an FSL, can I not connect just the uB side as buses in XPS and declare the other side as external ports

so that I can bring this out of uB instantation to my fpga logic (using ISE flow and xps as submodule) ?


When I do this and run XST, I get error messages that bus on the non-UB side are not connected.

 

Any ideas ?  ( I am using 10.1sp1)

 

 

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10 Replies
Visitor eliezerm
Visitor
14,766 Views
Registered: ‎04-15-2008

Re: FSL and bus vs ports

hello,

don't use FSL

create a core with no bus using a simple mpd file

 

Eliezer 

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Visitor sssingh
Visitor
14,750 Views
Registered: ‎04-27-2008

Re: FSL and bus vs ports

Why do you say, don't use FSL ?

FSL are like fifos (easiest to use).

My beef is the use model (outside of XPS) is not so obvious.  In the FSL mpd file, it

specifies that interface type is bus.

 

 

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Visitor eliezerm
Visitor
14,734 Views
Registered: ‎04-15-2008

Re: FSL and bus vs ports

sorry,

I didn't understand your question at first time.

can you send the mpd + vhd files of the core?

 

I think there is a guide somewhere about how to add a port to a core.

 

Eliezer 

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Xilinx Employee
Xilinx Employee
14,718 Views
Registered: ‎08-06-2007

Re: FSL and bus vs ports

Hi,

 

You can't make a bus as an external port in EDK.

You have to either

Connect each signal in the bus as external port

or

Make a pass-through pcore that takes the FSL bus and split it up to individual signals and make these external ports.

 

Göran

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Scholar golson
Scholar
14,699 Views
Registered: ‎04-07-2008

Re: FSL and bus vs ports

Do you have a example of how to create external port for a FSL user core?

Thank you,

  Gary Olson

 

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Visitor sssingh
Visitor
14,690 Views
Registered: ‎04-27-2008

Re: FSL and bus vs ports

Goran,

 

I have made a custom IP core (FSL).  It has 1 MFSL (master) and 1 SFSL (slave).

In the example created by the tool which sums the inputs, there is a place holder where

custom ports can be added.  In this custom fsl mpd, I see bus as the interface. 

 

So you are saying to add external ports to create the pass thru.  What I am missing, is

if I add ports to my verilog custom ip .v file, do I need to add these port myself to the

associated mpd file or is it automatic ?

 

If mpd can be edited by the user, which doc specifies all the options to write up a mpd ?

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Scholar golson
Scholar
14,678 Views
Registered: ‎04-07-2008

Re: FSL and bus vs ports

I found a document UG131 which might be of help to you.  Take a look on Page 40 at IO Interface.  It appears to me this might explain

that IO_IF and IO_IS tags are important for Ecternal Output ports.

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Scholar golson
Scholar
14,649 Views
Registered: ‎04-07-2008

Re: FSL and bus vs ports

Through web search you might find this informative.

 

http://www.groupsrv.com/computers/about283786.html

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Scholar golson
Scholar
14,608 Views
Registered: ‎04-07-2008

Re: FSL and bus vs ports

I am trying to do similar things to what you are doing I am a newbie, buit I have passed some of the hurdles.  You can do the following to get through creating a net list.

Yes, You have to edit files. including the MPD file of your peripheral and the MHS file.  In the Peripheral MPD file I had added one external port I called it UART_OUT.

 

SO I had to add to my MPD File a line to indicate I had a PORT.  Here is my MPD File:

 

BEGIN my_oeriph

## Peripheral Options

OPTION IPTYPE = PERIPHERAL

OPTION IMP_NETLIST = TRUE

OPTION HDL = VHDL

## Bus Interfaces

BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=SLAVE

## Peripheral ports

PORT FSL_Clk = "", DIR=I, SIGIS=Clk, BUS=SFSL

PORT FSL_Rst = OPB_Rst, DIR=I, BUS=SFSL

PORT FSL_S_Clk = FSL_S_Clk, DIR=O, SIGIS=Clk, BUS=SFSL

PORT FSL_S_Read = FSL_S_Read, DIR=O, BUS=SFSL

PORT FSL_S_Data = FSL_S_Data, DIR=I, VEC=[0:31], BUS=SFSL

PORT FSL_S_Control = FSL_S_Control, DIR=I, BUS=SFSL

PORT FSL_S_Exists = FSL_S_Exists, DIR=I, BUS=SFSL

PORT UART_OUT = UART_OUT, DIR=O

END

 

The last line before end is the line I added.

 

Then On the MHS File I did the following:

 

At the top of the MHS file are the external ports listed I added at the end of the list my external port:

 

PORT UART_OUT = UART_OUT, DIR = O

 

 

Then in the Microblase instantiation region It looks like the following:

 

 

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER HW_VER = 7.10.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_FSL_LINKS = 2
# PARAMETER C_FSL_DATA_SIZE = 32
 BUS_INTERFACE MFSL0 = fsl_v20_0
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 PORT MB_RESET = mb_reset
 PORT Interrupt = Interrupt
END

 

The main thing here is I have one interface to my peripheral.  Not two examples I have seen.  So I have just one statement

 

BUS_INTERFACE MFSL0 = fsl_v20_0

 

The right side is the instantiated FSL interface lower in the file:  This will wire up the FSL to the microblaze.  And you will be able to see the wire in the block diagram hooked up.

 If you did not put this in there the Block diagram will show a gap in the Master FSL port wire and you can tell it has not been wired up.

 

The next section you have to change is your peripheral instantiation.  Here is mine

 

BEGIN my_oeriph
 PARAMETER INSTANCE = my_oeriph_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SFSL = fsl_v20_0
 PORT UART_OUT = UART_OUT
END

 

 

Notice the statement BUS_INTERFACE SFSL = fsl_V20_0 

This is the same Idea as the Micro region.  This statement hooks up the Slave FSL to the instance of the FSL port that is below in the file.

 

Also notice my Port Name in my peripheral region

 

PORT UART_OUT = UART_OUT

This should allow the port to be available outside the instance.

 

Finally  The last region is my FSL instantiation.  In my design I only want one FSL.  Others want more.

 Here is my FSL Instantiation.

 

BEGIN fsl_v20

PARAMETER INSTANCE = fsl_v20_0

PARAMETER HW_VER = 2.11.a

PARAMETER C_EXT_RESET_HIGH = 1

PARAMETER C_FSL_DWIDTH = 32

PARAMETER C_FSL_DEPTH = 1024

PARAMETER C_USE_CONTROL = 0

PORT FSL_Clk = sys_clk_s

PORT FSL_Rst = sys_rst_s

END

 

 

The main thing I added here was 

PORT FSL_Clk = sys_clk_s 

PORT FSL_Rst = sys_rst_s

PARAMETER C_FSL_DEPTH = 1024

PARAMETER C_FSL_DEPTH = 1024

PARAMETER C_USE_CONTROL = 0

 

That is I wired up clock and reset. I changed my FIFO Depth to 1024 to match what I

created the fifo depth to be at the beginning of creating my peripheral.

 

After I did these things I have been able to create a netlist.

 

Thank You,

  Gary Olson

 

 

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Scholar golson
Scholar
4,843 Views
Registered: ‎04-07-2008

Re: FSL and bus vs ports

I did find a problem with what I did.

 

I have an error:

 

 Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"

xst -ifn system_xst.scr -intstyle silent
Running XST synthesis ...

ERROR:Xst:528 - Multi-source in Unit <system> on signal <sys_rst_pin>; this signal is connected to multiple drivers.

make: *** [implementation/system.ngc] Error 1

 

I hooked up sys_rst_s to a output by mistake.  Need to figure out what I am supposed to do with this.

 

 

 

 

entity fsl_v20_0_wrapper is

port (

FSL_Clk : in std_logic;

SYS_Rst : in std_logic;

FSL_Rst : out std_logic;

FSL_M_Clk : in std_logic;

FSL_M_Data : in std_logic_vector(0 to 31);

FSL_M_Control : in std_logic;

FSL_M_Write : in std_logic;

FSL_M_Full : out std_logic;

FSL_S_Clk : in std_logic;

FSL_S_Data : out std_logic_vector(0 to 31);

FSL_S_Control : out std_logic;

FSL_S_Read : in std_logic;

FSL_S_Exists : out std_logic;

FSL_Full : out std_logic;

FSL_Has_Data : out std_logic;

FSL_Control_IRQ : out std_logic

);

 

 

 

The Region

 

BEGIN fsl_v20

PARAMETER INSTANCE = fsl_v20_0

PARAMETER HW_VER = 2.11.a

PARAMETER C_EXT_RESET_HIGH = 1

PARAMETER C_FSL_DWIDTH = 32

PARAMETER C_FSL_DEPTH = 1024

PARAMETER C_USE_CONTROL = 0

PORT FSL_Clk = sys_clk_s

PORT FSL_Rst = sys_rst_s

END

 

I hooked up FSL_Rst = sys_rst_s  this must be wrong because sys_rst_s is from the input pin and FSL_Rst is a output.

 

I think I need to change this

 

PORT FSL_Rst = sys_rst_s

 

to this:

 

PORT SYS_Rst  = sys_rst_s

 

 

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