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Contributor
Contributor
6,948 Views
Registered: ‎10-09-2009

FSL speed problem

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Hi everyone,

 

in my design microblaze collect some data from DDR2 via mpmc and put it into fsl bus but, this process last for 280 clock periods and according to my design it must be max. 10 clock periods so any suggestions to speed it up?

 

my sw function to put fsl bus:

 

void ddr2fsl(u32 *Addr, u32 words)

{

    u32  i;

 

    for ( i=4;  i < words ; i++ )

 

    {

 

    putfsl(Addr[i],0); 

 

    } 

 

 

    thats it, just a for loop but it takes 280 clock periods...

 

any suggestions? 

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Xilinx Employee
Xilinx Employee
8,711 Views
Registered: ‎08-06-2007

Re: FSL speed problem

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Hi,

 

Any single word read from external memory takes > 25 clock cycles.

 

Using MicroBlaze as a DMA controller is not a good idea if you want to push the limits of the data bandwidth.

MicroBlaze isn't a particular fast DMA controller.

 

Some trick to make it faster:

- Use data cache if you haven't done it already

- Unroll the loop or write it in assembler

 

Göran

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5 Replies
Xilinx Employee
Xilinx Employee
8,712 Views
Registered: ‎08-06-2007

Re: FSL speed problem

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Hi,

 

Any single word read from external memory takes > 25 clock cycles.

 

Using MicroBlaze as a DMA controller is not a good idea if you want to push the limits of the data bandwidth.

MicroBlaze isn't a particular fast DMA controller.

 

Some trick to make it faster:

- Use data cache if you haven't done it already

- Unroll the loop or write it in assembler

 

Göran

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Contributor
Contributor
6,875 Views
Registered: ‎10-09-2009

Re: FSL speed problem

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Hi,

 

thanks for your feedback I've unrolled the loop now it takes 70 clock cycles. But I couldn't enable the data cache properly, when I enable the data cache and connect XCL interface I can't generate addresses it says there is a address confliction and if I change the default address value it cant generate netlist it can not generate mask for the LMB peripherals I've searched the forum about it but couldn't find a solution.

 

by the way I'm using lwip, xilkernel in software and ml506 in hardware

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Xilinx Employee
Xilinx Employee
6,871 Views
Registered: ‎08-06-2007

Re: FSL speed problem

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Hi,

 

Without caches, you will not get any performance, simple as that.

 

You can generate a dummy system using BSB which uses caches, take a look at the .mhs and see if you understand what is wrong with your system.

 

- Make sure that icache and dcache base/high address maps with the mpmc base/high address.

- You can leave the PLB port on MPMC. If you remove it make sure that you enable C_ICACHE_ALWAYS_USED and C_DCACHE_ALWAYS_USED on MicroBlaze

 

Göran

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Contributor
Contributor
6,847 Views
Registered: ‎10-09-2009

Re: FSL speed problem

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hi, thanks for your reply I've generated a new system with bsb it seems I've already managed to enable data cache, another peripheral was causing adress confliction.. so 70 cycle writing sequence is the best I can get but, still not enough.. it seems my project failed with ublaze thanks for your effort..
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Xilinx Employee
Xilinx Employee
6,842 Views
Registered: ‎08-06-2007

Re: FSL speed problem

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Hi,

 

70 cycles for sending 4 words to FSL sounds like the data isn't in the cache and that it needs to be fetch from external memory.

Furthermore if your 4 words isn't align to a cacheline, you will get two cache misses and this could explain the 70 clock cycles.

 

Göran

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