I'm working on a custom board based on ML507 with Virtex - 5.
I'm working with Spansion flash S29GL-P, 1 Gb / 128 MB.
My problem is that when the FPGA start up in BPI up mode, it looks for the configuration file in the flash at address 0xC00000 instead at 0 address.
The address bus is 26 bits, this means pins 22 and 23 are driven high somehow.
As shown in the picture I've uploaded, address lines 22 and 23 are connected same as in ML507.
My question is how can I control the RS pins to stay low, I already have a pulldown on this lines, should I strengthen it?
Thanks a lot.