Has any one measured the cycles needed for a single I/O function using a GPIO peripheral with the PowerPC processor (Virtex-II Pro device). I have measured using a counter and i takes 115 cycles. I think these are a lot of cycles. Is there anything I can do to reduce the cycles?
The performance can vary quite a bit depending on where you are executing your code (ie DDR, BRAM, OCM, etc) and how many clocks cycles it takes to execute your code.
You can expect to see a delay of about 50 clock cycles when executing the code out of PLB BRAM. You can increase your performance the most by optimizing your code (ie as few as instructions as possible, using pointers is probably the best for writing/reading to GPIO) and by using local memory (ie OCM, BRAM) as opposed to DDR.
Once the GPIO address is presented on the PLB bus it will take approximately 12 clocks before you see the output on the GPIO port. This includes delay from the PLB bus, PLB2OPB Bridge, and OPB bus. This performance can be improved by putting the GPIO on the PLB bus, this will save you approximately 8 clocks cycles.
I had an improvement by using an OCM controller for the instruction memory (fitted in BRAMs). Now it takes 63 cycles for an I/O instruction. I am using the xgpio.h library and the XGpio_mSetDataReg() to output data to the OPB GPIO peripheral. Is there anything else I can do to speed up my I/O functions form the programmin side? It also takes 83 cycles to read from a DDR memory that is installed in my board.
Dear xilant, you have given me the same reply in the old Xilinx forums. Where can I find others drivers for PowerPC 405? I don't want to pay for them. My project is for my Msc thesis, so I have no money to spend!