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Observer luis.munoz
Observer
6,964 Views
Registered: ‎10-08-2009

GPIO to FPGA FRABIC

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Hi guys,

 

how do I use the AXI GPIO to drive frabic logic rather than the signals going to the FPGA pads/pins.

 

I see that in the toplevel vhdl of the microblaze, usually system.vhd, it creates IO buffers for the GPIO. This creates problem when trying to drive frabic logic.

 

Does anyone know how to remove these IO buffers or some other work around?

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1 Solution

Accepted Solutions
Explorer
Explorer
8,932 Views
Registered: ‎08-02-2007

Re: GPIO to FPGA FRABIC

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you have to pull out the signals in the MHS file. Instead of using

 

PORT GPIO = my_gpio_port

 

You have to instead pull out all three signals individually

 

PORT GPIO_IO_T = my_tri_out_sig

PORT GPIO_IO_I = my_data_in_sig

PORT GPIO_IO_O = my_data_out_sig

 

So you are not connecting the pins, but instead individual inputs and outputs.  In your declaration you have declared the T signal as an 'inout' when it should really just be a an output as it is declared in the axi_gpio MPD file:

 

PORT GPIO_IO_I = "", DIR = I, VEC = [(C_GPIO_WIDTH-1):0], ENDIAN = LITTLE, IO_IF = gpio_0, IO_IS = gpio_data_in
PORT GPIO_IO_O = "", DIR = O, VEC = [(C_GPIO_WIDTH-1):0], ENDIAN = LITTLE, IO_IF = gpio_0, IO_IS = gpio_data_out
PORT GPIO_IO_T = "", DIR = O, VEC = [(C_GPIO_WIDTH-1):0], ENDIAN = LITTLE, IO_IF = gpio_0, IO_IS = gpio_tri_out

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7 Replies
Xilinx Employee
Xilinx Employee
6,956 Views
Registered: ‎07-30-2007

Re: GPIO to FPGA FRABIC

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Connect your fabric logic to the GPIO_I/_O/_T signals instead. These stand for the input/output/tristate signals associated with the GPIO.
Observer luis.munoz
Observer
6,937 Views
Registered: ‎10-08-2009

Re: GPIO to FPGA FRABIC

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How do I connect to those signals?

 

 

 

 COMPONENT micro1
 PORT(
  CLK_P : IN std_logic;
  CLK_N : IN std_logic;
  RS232_Uart_1_sin : IN std_logic;
  GPIO_T_pin : INOUT std_logic_vector(32 downto 0);
  RS232_Uart_1_sout : OUT std_logic;
  );
 END COMPONENT;

 

 

 

 

that is what I get from microblaze. If I connect GPIO_T_pin to a fabric logic I get an error, because within that component those signals are already connected to buffers

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Explorer
Explorer
8,933 Views
Registered: ‎08-02-2007

Re: GPIO to FPGA FRABIC

Jump to solution

you have to pull out the signals in the MHS file. Instead of using

 

PORT GPIO = my_gpio_port

 

You have to instead pull out all three signals individually

 

PORT GPIO_IO_T = my_tri_out_sig

PORT GPIO_IO_I = my_data_in_sig

PORT GPIO_IO_O = my_data_out_sig

 

So you are not connecting the pins, but instead individual inputs and outputs.  In your declaration you have declared the T signal as an 'inout' when it should really just be a an output as it is declared in the axi_gpio MPD file:

 

PORT GPIO_IO_I = "", DIR = I, VEC = [(C_GPIO_WIDTH-1):0], ENDIAN = LITTLE, IO_IF = gpio_0, IO_IS = gpio_data_in
PORT GPIO_IO_O = "", DIR = O, VEC = [(C_GPIO_WIDTH-1):0], ENDIAN = LITTLE, IO_IF = gpio_0, IO_IS = gpio_data_out
PORT GPIO_IO_T = "", DIR = O, VEC = [(C_GPIO_WIDTH-1):0], ENDIAN = LITTLE, IO_IF = gpio_0, IO_IS = gpio_tri_out

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Visitor jdkirby
Visitor
6,720 Views
Registered: ‎04-05-2011

Re: GPIO to FPGA FRABIC

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This doesn't quite work.

 

Doing this inside XPS 12.4 results in the following error:

 

ERROR:EDK:1525 - INST:axi_gpio_0 PORT:GPIO_IO_I -
   C:\xxx_xxxxxxxx\xxxxx_xxxxx_xxxxx_FPGA\system\system.mhs line 426 - port is
   driven by a sourceless connector

Any ideas? I need this to connect to a black box component inside ISE that will be implemented at a later date. At this point the system.vhd and system_stub.vhd don't have the proper ports listed to do that.

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Explorer
Explorer
6,711 Views
Registered: ‎08-02-2007

Re: GPIO to FPGA FRABIC

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the error is telling you that you don't have a port connected for the GPIO_IO_I signal.  For example you have:

 

BEGIN instance axi_gpio_0

...

PORT GPIO_IO_I = GPIO_INPUT

...

END

 

But now you have to have a top level port that connects to this signal, or some other internal driver that is not getting optimized out of the design.   So you could have a top level port (from the EDK design perspective) that connects to your GPIO_INPUT signal or whatever it is that you have called this signal.

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Visitor jdkirby
Visitor
6,708 Views
Registered: ‎04-05-2011

Re: GPIO to FPGA FRABIC

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This description is rather incomplete.

 

You do need to edit the .MHS file as stated.

You also need to edit the system.vhd file and look for the axi-gpio_0 : axi_gpio_0_wrapper

edit the IO_I, IO_O, IO_T entries to connect to signals you desire

i.e. 

      GPIO2_IO_I => net_gnd18,
      GPIO2_IO_O => axi_gpio_0_GPIO2_IO_O,
      GPIO2_IO_T => open
The go to entity section and add:
axi_gpio_0_GPIO2_IO_O : out std_logic_vector(17 downto 0)
so the signal can get out of the system.vhd file.
You then need to bring this signal out to the ise_top.vhd file where you can route it to the component that needs it.
The real issue is once you do this you can't run XPS again or ALL your manual changes will be lost.
Ths is something the XPS tool should be doing automatically. Xilinx really dropped the ball here.
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Highlighted
Explorer
Explorer
6,704 Views
Registered: ‎08-02-2007

Re: GPIO to FPGA FRABIC

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You're not supposed to edit the system.vhd file as that file is auto generated by EDK.  If the axi_gpio_0_GPIO2_IO_0 signal is not getting routed to the top level port in your system.vhd file, it's probably because you didn't add a top level port that connects to this signal. You still have to add the following to the top of your MHS file:

 

PORT axi_gpio_0_GPIO2_IO_0_pin  = axi_gpio_0_GPIO2_IO_0, DIR = O

 

The EDK tools don't just automatically wrap some signal to the top level.  You have to tell it which signals you want at the top level of the EDK project.

 

If you have already done the above declaration or something similar in your EDK project MHS file, then please feel free to open a webcase so that we can further review the design.

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