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Observer
Observer
6,085 Views
Registered: ‎06-03-2010

Generate Bitstream error in XPS

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Hi

 

I am using XPS to implement VSK Lab 6 solution into the board. There is no errors or warnings when Building the project. However, when I Generate bitstream, there are 4 errors.

 

 

Here are the errors:

 

ERROR:ConstraintSystem:58 - Constraint <INST
   "clock_generator*using_dcm_module_inst*DCM_SP" LOC = DCM_X1Y0;>
   [system.ucf(18)]: INST "clock_generator*using_dcm_module_inst*DCM_SP" does
   not match any design objects.

 

 


ERROR:ConstraintSystem:59 - Constraint <NET dvi_out_reset_n   LOC = AD15 |>
   [system.ucf(231)]: NET "dvi_out_reset_n" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

 

 


ERROR:ConstraintSystem:59 - Constraint <SLEW=SLOW |> [system.ucf(231)]: NET
   "dvi_out_reset_n" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

 

 


ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD=LVCMOS33;> [system.ucf(231)]:
   NET "dvi_out_reset_n" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

 

 


ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1

 

 

 

 

Does anyone know how to correct the errors?

 

Thanks.

XPS generate bitstream for lab 6.JPG
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1 Solution

Accepted Solutions
Highlighted
7,456 Views
Registered: ‎10-10-2010

For the first error:

You should use clock_generator 1.00.a (find it here: http://forums.xilinx.com/t5/EDK-and-Platform-Studio/need-quot-clock-generator-1-00-a-quot/m-p/44993  then copy it to your project folder or to "installed folder"\EDK\hw\XilinxProcessorIPLib\pcores). After that, you change the version of clock_generator in the project system.mhs file to 1.00.a.

 

For the second error:

In the project's system.mhs, change " PORT dvi_out_reset_n = chrontel_rst, DIR = O, VEC = [0:0]" to "PORT dvi_out_reset_n = chrontel_rst, DIR = O"

 

I got the same errors before and that the way I fix it. Hope it works in your case.

View solution in original post

1 Reply
Highlighted
7,457 Views
Registered: ‎10-10-2010

For the first error:

You should use clock_generator 1.00.a (find it here: http://forums.xilinx.com/t5/EDK-and-Platform-Studio/need-quot-clock-generator-1-00-a-quot/m-p/44993  then copy it to your project folder or to "installed folder"\EDK\hw\XilinxProcessorIPLib\pcores). After that, you change the version of clock_generator in the project system.mhs file to 1.00.a.

 

For the second error:

In the project's system.mhs, change " PORT dvi_out_reset_n = chrontel_rst, DIR = O, VEC = [0:0]" to "PORT dvi_out_reset_n = chrontel_rst, DIR = O"

 

I got the same errors before and that the way I fix it. Hope it works in your case.

View solution in original post