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Newbie
Newbie
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Registered: ‎10-30-2007

Good day!?xml:namespace prefix = o ns = "urn:schemas...

Good day!

 

Please, answer my question.

 

Is it possible to organize the mode XCL Cacheline write (read) operation with 16-bit RAM in the controller MCH OPB EMC?

 

As written in the manual, there is no formal limitations for this mode (parameters C_XCLx_WRITEXFER, C_INCLUDE_DATAWIDTH_MATCHING must (may) be installed independently from parameter C_MAX_MEM_WIDTH). But in numerous examples in this documentation such mode is absent. Only two kinds of exchange were demonstrated in numerous examples:

1) XCL Cacheline write (read) operation with 32-bit RAM;

2) XCL Single write (read) operation with 8-bit RAM.

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