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Visitor rkndaiict
Visitor
4,109 Views
Registered: ‎07-09-2009

Having problem in Build All User Applications.....

Hi,

    I m having the following problem in creating WebServer on Spartan3E in Build All User Applications..

 

    /cygdrive/d/rahul/web_server_12/microblaze_0/libsrc/lwip_v3_00_a/src/contrib/ports/xilinx/netif/xemacliteif.c:416: undefined reference to `enable_interrupt'
    collect2: ld returned 1 exit status
    make: *** [Web_Server/executable.elf] Error 1 

 

 

I have connected all libraries -llwip4 and -lxilkernel. this problem occurs during Build All User Applications. I m not getting why this is happening???Please help me out...

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4 Replies
4,098 Views
Registered: ‎08-21-2008

Re: Having problem in Build All User Applications.....

Hello.

If you can paste your MHS file here for reference it will convinient to debug. 

Best of luck.
--
Unlimited in my Limits.
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Visitor rkndaiict
Visitor
4,090 Views
Registered: ‎07-09-2009

Re: Having problem in Build All User Applications.....

Fine Sire,

 


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1 Build EDK_K.15
# Fri Jul 10 01:16:18 2009
# Target Board:  Xilinx Spartan-3E Starter Board Rev D
# Family:    spartan3e
# Device:    XC3S500e
# Package:   FG320
# Speed Grade:  -4
# Processor: microblaze_0
# System clock frequency: 50.00 MHz
# On Chip Memory :   8 KB
# Total Off Chip Memory :  64 MB
# - DDR_SDRAM =  64 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I
 PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
 PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC = [0:7]
 PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin = fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3]
 PORT fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O, DIR = IO
 PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [15:0]
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER HW_VER = 7.10.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_AREA_OPTIMIZED = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 PORT MB_RESET = mb_reset
 PORT Interrupt = Interrupt
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.02.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_DCE
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_DCE_RX
 PORT TX = fpga_0_RS232_DCE_TX
END

BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END

BEGIN xps_gpio
 PARAMETER INSTANCE = DIP_Switches_4Bit
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x81420000
 PARAMETER C_HIGHADDR = 0x8142ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR_SDRAM
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_NUM_PORTS = 1
 PARAMETER C_MEM_PARTNO = MT46V32M16-6
 PARAMETER C_SPECIAL_BOARD = S3E_STKIT
 PARAMETER C_MEM_BANKADDR_WIDTH = 2
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_MEM_DQS_WIDTH = 2
 PARAMETER C_MEM_DM_WIDTH = 2
 PARAMETER C_MEM_TYPE = DDR
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
 PARAMETER C_SPLB0_NATIVE_DWIDTH = 32
 PARAMETER C_MPMC_BASEADDR = 0x8c000000
 PARAMETER C_MPMC_HIGHADDR = 0x8fffffff
 BUS_INTERFACE SPLB0 = mb_plb
 PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
 PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
 PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
 PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
 PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
 PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
 PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
 PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
 PORT MPMC_Clk0 = DDR_SDRAM_mpmc_clk_s
 PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
 PORT MPMC_Rst = sys_periph_reset
END

BEGIN xps_ethernetlite
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_SPLB_CLK_PERIOD_PS = 20000
 PARAMETER C_BASEADDR = 0x81000000
 PARAMETER C_HIGHADDR = 0x8100ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 50000000
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT1_FREQ = 100000000
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = DCM0
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT2_PHASE = 90
 PARAMETER C_CLKOUT2_GROUP = DCM0
 PORT CLKOUT0 = sys_clk_s
 PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s
 PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Irq = Interrupt
 PORT Intr = Ethernet_MAC_IP2INTC_Irpt
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Interrupt = xps_timer_1_Interrupt
END

 

Please help me out....

Thnx  

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Visitor rkndaiict
Visitor
4,067 Views
Registered: ‎07-09-2009

Re: Having problem in Build All User Applications.....

hay buddy i hav got d solution of my problem...If anyone having same problem please mail me or post d query......
0 Kudos
4,061 Views
Registered: ‎08-21-2008

Re: Having problem in Build All User Applications.....

Hello.

Clearly its visible in your MHS file that xps_timer interrupt you have not mapped in xps_intc.

Good that you got the solution. Is it the same thing or something else? 

Best of luck.
--
Unlimited in my Limits.
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