The interrupt return address (the PC associated with the instruction in the decode stage at the time of the interrupt) is automatically loaded into general purpose register R14. In addition, the processor also disables future interrupts by clearing the IE bit in the MSR. The IE bit is automatically set again when executing the RTID instruction.
I guess that probably you can just check the MSR register, unless you perform IE disabling out of that context.
Ibai Don’t forget to reply, kudo, and accept as solution.