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Registered: ‎07-23-2019

How do I merge ELF and BIT into a configuration file with ZynqUltrascale+?

 

I have some firmware and software that I can configure the FPGA with using JTAG. Now I have problems creating a config file for the flash...

First, in Vivado I tried Tools -> Associate ELF files

with this error:

error1.png

But there is! The Zynq MP is instantiated in a block design!

I found it's possible to add the ELF to the project as a source, but I'm not sure if it will be properly associated with the processor, will it?

 

Another thing I tried was Tools -> Generate memory configuration file. Then I have two problems:

a) I can only choose bit files, not ELF

b) It doesn't generate for dual qspi, why?

error 2.png

 

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Registered: ‎09-12-2007

Re: How do I merge ELF and BIT into a configuration file with ZynqUltrascale+?

Associating the ELF files is used to place an ELF into a Microblaze Application memory (LMB bram, or AXI bram). So, this is why you get the error here.

 

If you are targgeting the SRM processor on the PSU and want to add the ELF, then you will need to add this ELF to the boot partition. The FSBL (First Stage Bootloader_ will be executed, this will load all the images in the boot partition (user can create this in SDK), and will handoff execution (in your case to your elf)

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1209-embedded-design-tutorial.pdf

See Chapter 5

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