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Visitor
Visitor
5,098 Views
Registered: ‎09-06-2008

How to add DDR_DQ as DATA ports of ChipScope_ILA?

I had a problem when I was debugging the DDR SDRAM on our custom board.

I am using EDK 8.2i together with Chipscope 8.2

My project is using Microblaze and OPB DDR controller and a chipscope_ila ip.

 

I have tried RAS, CAS as the trigger ports of chipscope_ila.

But I couldn't add DDR_DQ as DATA ports of chipscope_ila. Maybe because DDR_DQ is a bi-directional IO port?

When generate bitstream, some errors occurs:

 

ERROR:MDT - fpga_0_DDR_SDRAM_16Mx32_DDR_DQ (fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_pin)
   - D:\Project\lab\system.mhs line 33 - multiple drivers found on the
   connection!
ERROR:MDT - fpga_0_DDR_SDRAM_16Mx32_DDR_DQ (DDR_DQ) - D:\Project\lab\system.mhs
   line 196 - multiple drivers found on the connection!
ERROR:MDT - fpga_0_DDR_SDRAM_16Mx32_DDR_DQ (DATA) - D:\Project\lab\system.mhs
   line 293 - multiple drivers found on the connection!
ERROR:MDT - fpga_0_DDR_SDRAM_16Mx32_DDR_DQ (DATA) - D:\Project\lab\system.mhs
   line 293 - connector is connected to both uni and bi-directional ports!

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

*************************************************************
Successfully generated the Chipscope Core : chipscope_opb_iba_0
*************************************************************
ERROR:MDT - platgen failed with errors!

 

 

This is the description about chipscope_ila in system.mhs file:

 

BEGIN chipscope_ila
 PARAMETER INSTANCE = chipscope_ila_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_TRIG0_UNITS = 1
 PARAMETER C_NUM_DATA_SAMPLES = 512
 PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 1
 PARAMETER C_DATA_IN_WIDTH = 48
 PARAMETER C_DATA_SAME_AS_TRIGGER = 0
 PARAMETER C_TRIG0_UNIT_MATCH_TYPE = basic with edges
 PARAMETER C_ENABLE_TRIGGER_OUT = 0
 PARAMETER C_ENABLE_TRIGGER_SEQUENCER = 0
 PARAMETER C_ENABLE_STORAGE_QUALIFICATION = 0
 PARAMETER C_TRIG1_UNITS = 1
 PARAMETER C_TRIG1_TRIGGER_IN_WIDTH = 1
 PARAMETER C_TRIG1_UNIT_MATCH_TYPE = basic with edges
 PARAMETER C_TRIG2_UNITS = 1
 PARAMETER C_TRIG2_TRIGGER_IN_WIDTH = 1
 PARAMETER C_TRIG2_UNIT_MATCH_TYPE = basic with edges
 PORT chipscope_ila_control = chipscope_ila_0_icon_control
 PORT CLK = sys_clk_s
 PORT TRIG0 = chipscope_opb_iba_0_iba_trig_out
 PORT TRIG1 = fpga_0_DDR_SDRAM_16Mx32_DDR_RASn
 PORT TRIG2 = fpga_0_DDR_SDRAM_16Mx32_DDR_CASn
 PORT DATA = fpga_0_DDR_SDRAM_16Mx32_DDR_Addr & fpga_0_DDR_SDRAM_16Mx32_DDR_DQ & fpga_0_DDR_SDRAM_16Mx32_DDR_WEn & fpga_0_DDR_SDRAM_16Mx32_DDR_CASn & fpga_0_DDR_SDRAM_16Mx32_DDR_RASn
END

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4 Replies
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Professor
Professor
5,087 Views
Registered: ‎08-14-2007

Re: How to add DDR_DQ as DATA ports of ChipScope_ILA?

The short answer is that you cannot add I/O pad nets to the ChipScope.  You need to find the

name of the nets after the input buffer (or in this case more likely after the input register) and

then you can add that to ChipScope.  You won't be able to debug sampling timing issues

with ChipScope very easily, if that's why you're trying to look at these signals.  Remember that

ChipScope also registers the data on its clock, so to be useful you need to use a clock

related to the DQ data sampling.

 

HTH,

Gabor

-- Gabor
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Visitor
Visitor
5,077 Views
Registered: ‎09-06-2008

Re: How to add DDR_DQ as DATA ports of ChipScope_ILA?

Thank you for your replay, I likely know what you mean. Then , I do something as follow:

 

1. Run through "generate netlist".

2. Open the system.vhd in "hdl" directory

3. Search for the net "DDR_DQ", and I found these,

signal fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_O : std_logic_vector(0 to 31);

signal fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_T : std_logic_vector(0 to 31);

 

iobuf_4 : IOBUF
    port map (
      I => fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_O(0),
      IO => fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_pin(0),
      O => fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_I(0),
      T => fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_T(0)
    );

I think these (fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_O) must be the nets after the IOBUF, so I connect it to the DATA port of chipscope_ila, but another errors happened:

ERROR: MDT - fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_O (DATA) - D:\Project\lab\system.mhs
   line 292 - connection has no driver!

 

Here is the system.mhs file:

external port:

PORT fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_pin = fpga_0_DDR_SDRAM_16Mx32_DDR_DQ, DIR = IO, VEC = [0:31]

 

BEGIN chipscope_ila
 PARAMETER INSTANCE = chipscope_ila_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_TRIG0_UNITS = 1
 PARAMETER C_NUM_DATA_SAMPLES = 512
 PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 1
 PARAMETER C_DATA_IN_WIDTH = 48
 PARAMETER C_DATA_SAME_AS_TRIGGER = 0
 PARAMETER C_TRIG0_UNIT_MATCH_TYPE = basic with edges
 PARAMETER C_ENABLE_TRIGGER_OUT = 0
 PARAMETER C_ENABLE_TRIGGER_SEQUENCER = 0
 PARAMETER C_ENABLE_STORAGE_QUALIFICATION = 0
 PARAMETER C_TRIG1_UNITS = 1
 PARAMETER C_TRIG1_TRIGGER_IN_WIDTH = 1
 PARAMETER C_TRIG1_UNIT_MATCH_TYPE = basic with edges
 PARAMETER C_TRIG2_UNITS = 1
 PARAMETER C_TRIG2_TRIGGER_IN_WIDTH = 1
 PARAMETER C_TRIG2_UNIT_MATCH_TYPE = basic with edges
 PORT chipscope_ila_control = chipscope_ila_0_icon_control
 PORT CLK = sys_clk_s
 PORT TRIG0 = chipscope_opb_iba_0_iba_trig_out
 PORT TRIG1 = fpga_0_DDR_SDRAM_16Mx32_DDR_RASn
 PORT TRIG2 = fpga_0_DDR_SDRAM_16Mx32_DDR_CASn
 PORT DATA = fpga_0_DDR_SDRAM_16Mx32_DDR_Addr & fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_O & fpga_0_DDR_SDRAM_16Mx32_DDR_WEn & fpga_0_DDR_SDRAM_16Mx32_DDR_CASn & fpga_0_DDR_SDRAM_16Mx32_DDR_RASn
END

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Highlighted
Xilinx Employee
Xilinx Employee
5,048 Views
Registered: ‎11-28-2007

Re: How to add DDR_DQ as DATA ports of ChipScope_ILA?

> I think these (fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_O) must be the nets after the IOBUF, so I connect it to the DATA port of chipscope_ila, but another errors happened:

 

I port of IOBUF is the nets BEFORE the IOBUF in that I ports drives IO port of IOBUF. If you want to check the data coming in from the IOBUF, you need to hook up the signal on the O port of IOBUF to the chipscope ila core. Having said that, it may not be a good idea to do that for a DDR controller as there may be speical data capture circuitry for DQ signals which requires exact placement and routing coming out of IOBUF to make the circuit to work.

 

 

 

 

Cheers,
Jim
ScreenHunter_04 Jan. 19 17.52.gif
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Highlighted
Visitor
Visitor
5,040 Views
Registered: ‎09-06-2008

Re: How to add DDR_DQ as DATA ports of ChipScope_ILA?

Actually, I want to check the data bus coming from the DDR SDRAM controller, but I don’t know which signal should I hook up to the DATA port of ChipScope ILA core. I have tried 3 signals: fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_O, fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_pin, fpga_0_DDR_SDRAM_16Mx32_DDR_DQ_T, but all encountered errors.

 

Another way I have tried is to use ChipScope Core Inserter to add ILA core in system.ngc, but there are also errors when placement and routing.

 

Can anyone give me a example project? Thank you.

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