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Participant rebakker
Participant
1,208 Views
Registered: ‎11-12-2014

How to configure Lwip for Microblaze with BRAM only?

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In the past I did a microblaze design for a Spartan-3A DSP using EDK 11.5 and Lwip 1.30 for UDP communication. The microblaze only used the 128kB internal BRAM as instruction and data memory. So no external DDR. And all worked well.

 

Today I'm doing a similar microblaze design for an Artix-7 using SDK 2018.1 and Lwip 2.02 for also UDP only communication. And again the microblaze should only use 128kB internal BRAM.

 

Now I'm in a continuous fight with the lwip202 BSP settings to fit an even smaller program into this 128kB memory. 

* Disabled LWIP_TCP

* Lowered PBUF_POOL_SIZE and PBUF_POOL_BUFSIZE

* Lowered MEM_SIZE to 32768

* Changed lwip202.tcl to get MEM_ALIGNMENT to 4 instead of 64. (@Xilinx: A microblaze is not the same as an UltraScale+ A53!).

 

How can this be fitted in a 128kB memory, and which settings could be tweaked? Or does there exist a modern example design?

 

 

 

 

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Participant rebakker
Participant
1,142 Views
Registered: ‎11-12-2014

Re: How to configure Lwip for Microblaze with BRAM only?

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To get a simple Lwip UDP echo server below 128kB I had to do the following:

 

Change the ‘Board Support Package Settings’ for lwip202

arp_options

  • arp_queueing = 0

dhcp_options

  • dhcp_does_arp_check = false
  • lwip_dhcp = false

lwip_ip_options

  • ip_frag = 0 (not so important)

lwip_memory_options

  • mem_size = 8192 (the actual needed amount can be observed using MEM_STATS_DISPLAY)
  • memp_n_pbuf = 0 (not needed)
  • memp_n_udp_pcb = 1 (only one udp pcb used)

pbuf_options

  • pbuf_pool_size = 16 (significant memory reduction)

tcp_options

  • lwip_tcp = false
  • tcp_queue_ooseq = 0

temac_adapter_options

  • n_rx_descriptors = 2 (significant memory reduction)
  • n_tx_descriptors = 2 (significant memory reduction)

udp_options

  • lwip_udp = true (used for the UDP echo server)

 

Changed MEM_ALIGNMENT assignement to 4 in Xilinx lwip202.tcl file in SDK \data\embeddedsw\ThirdParty\sw_service\lwip202_v1_0\data and regenerated BSP. The original memory alignment of 64 is because of the Ultrascale+ A53, and useless for a Microblaze. Insert the following at about line 543.

	switch -regexp $proctype {
            "microblaze" {
				puts $lwipopts_fd "\#define MEM_ALIGNMENT 4"
            }
            default {
				puts $lwipopts_fd "\#define MEM_ALIGNMENT 64"
            }
	}

The following can be placed in main.c to monitor this change.

#if MEM_ALIGNMENT != 4
#error "Change MEM_ALIGNMENT assignement to 4 in Xilinx lwip202.tcl file in SDK \data\embeddedsw\ThirdParty\sw_service\lwip202_v1_0\data and regenerate BSP."
#endif

Change PQ_QUEUE_SIZE to 64 in the BSP /microblaze_0/libsrc/lwip202_v1_0/src/contrib/ports/xilinx/include/netif/xpqueue.h. This gave a enormous memory size reduction and the originally 4096 deep queue is way too large for the limited amount of used pbufs. The following can be placed in main.c to monitor this change.

#include "netif/xpqueue.h"
#if PQ_QUEUE_SIZE != 64
#error "Change PQ_QUEUE_SIZE to 64 in project BSP /microblaze_0/libsrc/lwip202_v1_0/src/contrib/ports/xilinx/include/netif/xpqueue.h."
#endif

 

The stack and heap can also reduced in size.

 

With all this, it remains below 128kB and still works, when placing .bss still in DDR. Have not figured out yet how to get the AXI DMA with the AXI Ethernet working with LMB BRAM and BRAM shared memory only.

 

3 Replies
Moderator
Moderator
1,182 Views
Registered: ‎09-12-2007

Re: How to configure Lwip for Microblaze with BRAM only?

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You are unlikely to fit the lwip into 128KB bram
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Participant rebakker
Participant
1,143 Views
Registered: ‎11-12-2014

Re: How to configure Lwip for Microblaze with BRAM only?

Jump to solution

To get a simple Lwip UDP echo server below 128kB I had to do the following:

 

Change the ‘Board Support Package Settings’ for lwip202

arp_options

  • arp_queueing = 0

dhcp_options

  • dhcp_does_arp_check = false
  • lwip_dhcp = false

lwip_ip_options

  • ip_frag = 0 (not so important)

lwip_memory_options

  • mem_size = 8192 (the actual needed amount can be observed using MEM_STATS_DISPLAY)
  • memp_n_pbuf = 0 (not needed)
  • memp_n_udp_pcb = 1 (only one udp pcb used)

pbuf_options

  • pbuf_pool_size = 16 (significant memory reduction)

tcp_options

  • lwip_tcp = false
  • tcp_queue_ooseq = 0

temac_adapter_options

  • n_rx_descriptors = 2 (significant memory reduction)
  • n_tx_descriptors = 2 (significant memory reduction)

udp_options

  • lwip_udp = true (used for the UDP echo server)

 

Changed MEM_ALIGNMENT assignement to 4 in Xilinx lwip202.tcl file in SDK \data\embeddedsw\ThirdParty\sw_service\lwip202_v1_0\data and regenerated BSP. The original memory alignment of 64 is because of the Ultrascale+ A53, and useless for a Microblaze. Insert the following at about line 543.

	switch -regexp $proctype {
            "microblaze" {
				puts $lwipopts_fd "\#define MEM_ALIGNMENT 4"
            }
            default {
				puts $lwipopts_fd "\#define MEM_ALIGNMENT 64"
            }
	}

The following can be placed in main.c to monitor this change.

#if MEM_ALIGNMENT != 4
#error "Change MEM_ALIGNMENT assignement to 4 in Xilinx lwip202.tcl file in SDK \data\embeddedsw\ThirdParty\sw_service\lwip202_v1_0\data and regenerate BSP."
#endif

Change PQ_QUEUE_SIZE to 64 in the BSP /microblaze_0/libsrc/lwip202_v1_0/src/contrib/ports/xilinx/include/netif/xpqueue.h. This gave a enormous memory size reduction and the originally 4096 deep queue is way too large for the limited amount of used pbufs. The following can be placed in main.c to monitor this change.

#include "netif/xpqueue.h"
#if PQ_QUEUE_SIZE != 64
#error "Change PQ_QUEUE_SIZE to 64 in project BSP /microblaze_0/libsrc/lwip202_v1_0/src/contrib/ports/xilinx/include/netif/xpqueue.h."
#endif

 

The stack and heap can also reduced in size.

 

With all this, it remains below 128kB and still works, when placing .bss still in DDR. Have not figured out yet how to get the AXI DMA with the AXI Ethernet working with LMB BRAM and BRAM shared memory only.

 

Participant rebakker
Participant
1,124 Views
Registered: ‎11-12-2014

Re: How to configure Lwip for Microblaze with BRAM only?

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The block design I used is a copy of the AC701_AxiEth_100MHZ_32kb from xapp1026.

I first changed the 64kB LMB to 128kB.

 

Since the AXI Ethernet/DMA needs to transmit and receive data using the pbufs (descriptors), the DMA must be able to access the memory in which the pbufs (within section .bss) are located. If the .bss is located within the LMB BRAM the DMA can not access the memory which results is error messages (via the AXI Uartlite):

axidma_recv_handler: Error: axidma error interrupt is asserted

So the .bss can remain in the DDR and all other section can be moved to the LMB BRAM within the lscript.ld.

 

After this I changed the AC701_AxiEth_100MHZ_32kb design as follows:

  • Removed the LMB BRAM
  • Removed the Local Memory Bus Instruction Interface from the MicroBlaze
  • Removed the Local Memory Bus Data Interface from the MicroBlaze
  • Added Peripheral AXI Instruction interface to the MicroBlaze
  • Increased the shared BRAM to 128kB
  • Added an AXI interconnect and connected M00_AXI of it to the shared AXI BRAM Controller, connected the S00_AXI to M00_AXI of the 'axi_mem_intercon', and connected the S01_AXI to the M_AXI_IP of the MicroBlaze.
  • Assigned base address 0x00000000 to the shared BRAM
  • Excluded all peripherals from the Address Segments of the Instruction bus.
  • Synthesized en implemented the design
  • Updated the SDK hardware platform
  • Regenerated the Linker Script and place all section in the shared BRAM. (Heap and Stack can be about 1kB or 2kB)

And after this, all runs within the shared BRAM of 128kB.

 

Since the design is small and the number of available pbufs limited, this can be used behind an Ethernet switch which limits the traffic to the module to only the addressed broadcast, multicast and unicast communication.

 

BTW. Changing sizes of IP memories (and interrupt concats) within a block design which have been generated by the Vivado tcl scripts are often sort of locked because of some USER parameter which ought to be default. What ever that means. This can be overcome by manual replacing the IP memories. Changing the size can be done in the Address Editor.

 

The next step was to remove the DDR interface, and so I changed the following:

  • Remove the 'MIG 7 Series' IP and the DDR3 External Interface, and remove the M01_AXI interface from 'axi_mem_intercon'.
  • Changed clk_wiz_0 so sys_diff_clock is used as the input clock, clk_out1 (100MHz) for processor and AXI clk, clk_out2 (125MHz) AXI Ethernet gtx_clk, and clk_out3 (200MHz) to AXI Ethernet ref_clk. The locked output to dcm_locked of the Processor System Reset.
  • Connect the M00_AXI interface from 'axi_mem_intercon' directly to the shared BRAM, and remove the previously added AXI interconnect.
  • Remove Peripheral AXI Instruction interface from the MicroBlaze
  • Update the MicroBlaze Instruction and Data cache to interface on the shared BRAM at 0x0000000 with size 0x0001FFFF and limit the size to 4kB (one BRAM).

This reduces the overall design in size even further.

 

The AXI Ethernet TX Memory Size and RX Memory Size (both 32k within AC701_AxiEth_100MHZ_32kb) can also be reduced to 8k to free more BRAM resources. 8k is enough for several Ethernet packets, since this small LWIP implementation within 128kB does not support jumbo frames.

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