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sanchean
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Registered: ‎06-07-2018

How to configure lwIP for TCP/IP and Microblaze without external RAM

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Hello,

Following on this topic: Solved: Re: AXI EthernetLite -> Vitis errors with lwIP: "F... - Community Forums (xilinx.com),
I am trying now to configure the lwIP library for TCP/IP and a Microblaze system without external RAM.

I've found this thread to be very useful: Solved: How to configure Lwip for Microblaze with BRAM onl... - Community Forums (xilinx.com)
but I am now a bit lost with all the lwIP parameters of the BSP. I'm making my way through them but it is taking some time.

So I was wondering if anyone has succesfully modified and implemented the lwIP library in a Microblaze system with no external RAM?

Thanks in advance,
Andrés

1 Solution

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sanchean
Visitor
Visitor
54 Views
Registered: ‎06-07-2018

Hello again,

I've finally managed to configure lwIP with TCP (no DHCP and no UDP though) and implement it into a Microblaze system without external RAM, just a block RAM of 128K.
For the prove of concept I've implemented the design into an Arty development board (xc7a35ticsg324-1L) with Ethernet interface, using Vivado and Vitis 2020.2. I've used the example application project lwIP Echo Server as the Microblaze base design.

The purpose of the Microblaze system is to implement:

  • Modbus TCP/IP protocol: AXI EthernetLite + AXI Timers
  • UART communication with PC: AXI Uartlite
  • Access to logic external to the block design: AXI GPIOs

First, the Vivado project. This is the block design. The main clock sys_clock is a 100MHz clock and the 25 MHz Ethernet clock for the IC is generated and routed in the top level file.

sanchean_0-1632380952736.png

This is a snapshot of the Vivado address editor:

sanchean_2-1632381165083.png

The configuration of the main IP blocks is the following:

1. Microblaze

sanchean_3-1632381359630.png

 

sanchean_4-1632381371702.png

 

sanchean_5-1632381395227.png

 

sanchean_6-1632381406148.png

 

 

2. AXI EthernetLite

sanchean_7-1632381573789.png

3. AXI BRAM Controller

sanchean_8-1632381699295.png

4. Block Memory Generator:

  • Mode is BRAM Controller
  • Safety circuit disabled

Now, the Vitis project.

The first things to do, as explained by @rebakker in this thread Solved: How to configure Lwip for Microblaze with BRAM onl... - Community Forums (xilinx.com), are the following modifications:

1. Changed MEM_ALIGNMENT assignement to 4 in Xilinx lwip202.tcl file in SDK \data\embeddedsw\ThirdParty\sw_service\lwip202_v1_0\data and regenerated BSP. The original memory alignment of 64 is because of the Ultrascale+ A53, and useless for a Microblaze. Insert the following at about line 543.

	switch -regexp $proctype {
            "microblaze" {
				puts $lwipopts_fd "\#define MEM_ALIGNMENT 4"
            }
            default {
				puts $lwipopts_fd "\#define MEM_ALIGNMENT 64"
            }
	}

The following can be placed in main.c to monitor this change.

#if MEM_ALIGNMENT != 4
#error "Change MEM_ALIGNMENT assignement to 4 in Xilinx lwip202.tcl file in SDK \data\embeddedsw\ThirdParty\sw_service\lwip202_v1_0\data and regenerate BSP."
#endif

2. Change PQ_QUEUE_SIZE to 64 in the BSP /microblaze_0/libsrc/lwip202_v1_0/src/contrib/ports/xilinx/include/netif/xpqueue.h. This gave a enormous memory size reduction and the originally 4096 deep queue is way too large for the limited amount of used pbufs. The following can be placed in main.c to monitor this change.

#include "netif/xpqueue.h"
#if PQ_QUEUE_SIZE != 64
#error "Change PQ_QUEUE_SIZE to 64 in project BSP /microblaze_0/libsrc/lwip202_v1_0/src/contrib/ports/xilinx/include/netif/xpqueue.h."
#endif

Then we can proceed with the configuration of the lwip library:

sanchean_9-1632382080416.pngsanchean_10-1632382108299.png

 

 

The Stack and Heap size can also be reduced to 0x0400 in the Linker Script file.

To further reduce the size, we can add the compiler flag -Os (optimization for size), both for the BSP and the application project.

sanchean_11-1632382243808.png

sanchean_12-1632382289643.png

 

 

And I think that's it. If I forget anything I will update this post.

Cheers,
Andres

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sanchean
Visitor
Visitor
55 Views
Registered: ‎06-07-2018

Hello again,

I've finally managed to configure lwIP with TCP (no DHCP and no UDP though) and implement it into a Microblaze system without external RAM, just a block RAM of 128K.
For the prove of concept I've implemented the design into an Arty development board (xc7a35ticsg324-1L) with Ethernet interface, using Vivado and Vitis 2020.2. I've used the example application project lwIP Echo Server as the Microblaze base design.

The purpose of the Microblaze system is to implement:

  • Modbus TCP/IP protocol: AXI EthernetLite + AXI Timers
  • UART communication with PC: AXI Uartlite
  • Access to logic external to the block design: AXI GPIOs

First, the Vivado project. This is the block design. The main clock sys_clock is a 100MHz clock and the 25 MHz Ethernet clock for the IC is generated and routed in the top level file.

sanchean_0-1632380952736.png

This is a snapshot of the Vivado address editor:

sanchean_2-1632381165083.png

The configuration of the main IP blocks is the following:

1. Microblaze

sanchean_3-1632381359630.png

 

sanchean_4-1632381371702.png

 

sanchean_5-1632381395227.png

 

sanchean_6-1632381406148.png

 

 

2. AXI EthernetLite

sanchean_7-1632381573789.png

3. AXI BRAM Controller

sanchean_8-1632381699295.png

4. Block Memory Generator:

  • Mode is BRAM Controller
  • Safety circuit disabled

Now, the Vitis project.

The first things to do, as explained by @rebakker in this thread Solved: How to configure Lwip for Microblaze with BRAM onl... - Community Forums (xilinx.com), are the following modifications:

1. Changed MEM_ALIGNMENT assignement to 4 in Xilinx lwip202.tcl file in SDK \data\embeddedsw\ThirdParty\sw_service\lwip202_v1_0\data and regenerated BSP. The original memory alignment of 64 is because of the Ultrascale+ A53, and useless for a Microblaze. Insert the following at about line 543.

	switch -regexp $proctype {
            "microblaze" {
				puts $lwipopts_fd "\#define MEM_ALIGNMENT 4"
            }
            default {
				puts $lwipopts_fd "\#define MEM_ALIGNMENT 64"
            }
	}

The following can be placed in main.c to monitor this change.

#if MEM_ALIGNMENT != 4
#error "Change MEM_ALIGNMENT assignement to 4 in Xilinx lwip202.tcl file in SDK \data\embeddedsw\ThirdParty\sw_service\lwip202_v1_0\data and regenerate BSP."
#endif

2. Change PQ_QUEUE_SIZE to 64 in the BSP /microblaze_0/libsrc/lwip202_v1_0/src/contrib/ports/xilinx/include/netif/xpqueue.h. This gave a enormous memory size reduction and the originally 4096 deep queue is way too large for the limited amount of used pbufs. The following can be placed in main.c to monitor this change.

#include "netif/xpqueue.h"
#if PQ_QUEUE_SIZE != 64
#error "Change PQ_QUEUE_SIZE to 64 in project BSP /microblaze_0/libsrc/lwip202_v1_0/src/contrib/ports/xilinx/include/netif/xpqueue.h."
#endif

Then we can proceed with the configuration of the lwip library:

sanchean_9-1632382080416.pngsanchean_10-1632382108299.png

 

 

The Stack and Heap size can also be reduced to 0x0400 in the Linker Script file.

To further reduce the size, we can add the compiler flag -Os (optimization for size), both for the BSP and the application project.

sanchean_11-1632382243808.png

sanchean_12-1632382289643.png

 

 

And I think that's it. If I forget anything I will update this post.

Cheers,
Andres

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