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Contributor
Contributor
7,434 Views
Registered: ‎09-22-2015

How to constraint the BUFR--BUFG clocks ?

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HI:

  I am using BUFR with BUFG to generate a clock named clk_div2 divided by 2 from FCLK0(clk_fpga_0) in ZYNQ.

  Should I write constraints between clk_div2 and FCLK0 (clk_fpga_0)? Or the VIVADO can auto constraint the couple clocks so I do not to need to constraint them manually?

 If I constraint them manually , is it enough like this ?

 

create_generated_clock -name clk_div2_0 -source [get_pins design_1_i/ADC_UNION_64_PORTS/clk_o3_0/clk_div2] -divide_by 2 -add -master_clock clk_fpga_0 [get_pins design_1_i/ADC_UNION_64_PORTS/clk_o3_0/clk_div2]

 I get some inter-clock timing errors in the timing analysis like following ,how can I solve this ? Thanks very much!

 20160708094552.png

 
 

 

 

20160708095241.png

20160708095312.png

 

 

 

 

 
 
 
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Teacher
Teacher
13,167 Views
Registered: ‎03-31-2012
there is never a need to add constraints for any buffer elements (or pll/mmcm cells) through which the tool knows how to propagate timing.
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Moderator
Moderator
7,388 Views
Registered: ‎02-16-2010
The tool should generate the constraints for BUFR-> BUFG output. Please check this before adding manual constraint.
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Contributor
Contributor
7,350 Views
Registered: ‎09-22-2015

HI 

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Xilinx Employee
Xilinx Employee
7,219 Views
Registered: ‎08-01-2008

UG903 - Vivado Design Suite User Guide: Using Constraints ( ver2016.2, 5212 KB ) [PDF]

UG906 - Vivado Design Suite User Guide: Design Analysis and Closure Techniques ( ver2016.2, 8001 KB ) [PDF]

 

   
 
Thanks and Regards
Balkrishan
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Highlighted
Teacher
Teacher
13,168 Views
Registered: ‎03-31-2012
there is never a need to add constraints for any buffer elements (or pll/mmcm cells) through which the tool knows how to propagate timing.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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