cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
vineeshvs
Observer
Observer
1,160 Views
Registered: ‎11-26-2018

How to design a custom ip (axi compatible) to read and write from DDR

Hello all,

I have a design with Microblaze and MIG, which is tested through xsct for read and write from a 2GB DDR3 RAM.

I would like to design a custom IP which would take commands (for block read and write from memory) through xsct and write to the RAM as per the command.

Example: A command would ask the custom ip to do a block read (say from 128 locations) from a particular address.

Doubts

  1. Is Microblaze or any processor needed to achieve this objective?
  2. How can I design my custom IP (as I don't understand how Microblaze communicates with MIG). Where can I read about it? Or is it even necessary for this purpose?

Thanks :)

 

0 Kudos
5 Replies
xilinxacct
Professor
Professor
1,134 Views
Registered: ‎10-23-2018

@vineeshvs

As for your doubts... I don't see a 'need' for the MicroBlaze (unless something else in the design requires it). 

I would suggest you take a look at the IP catalog within Vivado in the AXI infrastucture section. You will see several 'memory' related items that use the AXI interface. Your custom logic would simply 'wrap' the call to this IP.

Hope that helps

0 Kudos
dgisselq
Scholar
Scholar
1,102 Views
Registered: ‎05-21-2015

No, you don't need a MicroBlaze.

I am the author and designer of the ZipCPU.  I've placed this CPU on the Arty A7 board sold by Digilent.  All of the logic necessary to read and write from the AXI port of the MIG DDR3 controller is available in this same project.  There's also setup instructions for how to configure the MIG for the DDR3 SDRAM on the Arty A7.  Most of the details within those instructions came from reading the XML within the Arty A7's project file.

The approach I used to do this was to bridge from a basic Wishbone bus to the AXI bus in order to read and write the DDR3 memory.  Why wishbone? Because its simpler than AXI.  That said, I'm not using any of the block read capabilities of AXI that you mentioned above, choosing instead to issue multiple independent commands sequentially to achieve the same effect.  The design does suffer a clock or two of latency for using this approach.

Hope this helps,

Dan

0 Kudos
stephenm
Xilinx Employee
Xilinx Employee
1,034 Views
Registered: ‎09-12-2007

Have a look at the jtag 2 AXI IP in the IP catalog. There are commands that yhou can use to do various bursts. This would prevent re-writing your own logic

0 Kudos
stephenm
Xilinx Employee
Xilinx Employee
1,032 Views
Registered: ‎09-12-2007

Have you documented the logic used to implement your zipcpu on an Arty board. 

0 Kudos
dgisselq
Scholar
Scholar
1,005 Views
Registered: ‎05-21-2015

@Anonymous,

"Have you documented the logic used to implement your ZipCPU on an Arty board" is a very broad question.  Much of the logic has been documented, yes.  I've been known to document various pieces on my zipcpu.com blog.  This includes the ZipCPU, its instruction set architecture, its verification approach, the various prefetches and ALU used within it, how I interpret the WB spec formally, and much more.  I'm hoping to blog about the caches in the near future, should the Lord be willing.

The OP asked about reading and writing from DDR SDRAM.  The documentation for the project itself, as found on the project page in the doc/ directory, discusses how to create a MIG component that the design will connect with.  The connection from WB to AXI is based around a WB to AXI bridge that has some amount of internal documentation within it as well, mostly at the top of the file.  Looking over it now, it could probably use some more documentation, but you are more then welcome to browse through it and see what you find.

Dan

0 Kudos