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Contributor
Contributor
6,761 Views
Registered: ‎09-15-2008

How to figure out the name of a clock net that needs constraining.

I'm finishing up a large XPS design with a lot of custom peripherals, and I've having a difficult time getting all my timing constraints written down in the UCF file. A lot of my peripherals contain internal clocks and other nets that need to be constrained, but which never leave the peripheral (some of them go up or down the submodule heirarchy within a peripheral).

 

The net names I assign them in Verilog don't seem to "stick" though. When the implementer is trying to parse the UCF file, it always complains that it can't find the nets I'm trying to attach timing constraints to. I would assume that means the synthesizer is changing the net names somewhere during synthesis.

 

How can I force the synthesizer to leave nets with a particular name so that I can constrain the timing?

 

Thanks,

Nick

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4 Replies
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Scholar
Scholar
6,745 Views
Registered: ‎04-07-2008

I you can use timing analyzer and more important tool would probably be the FPGA Editor in the XPS file to find the name of the signals you are looking for.

 

You can search this forum to find more info on both of these tools and how to use them.

 

 

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Highlighted
6,736 Views
Registered: ‎08-21-2008

Hello.

You can look out for the name after doing synthesis of your design. Look for the SRP file in the systhesis folder corresponding to your module. You will get it in that. 

Best of luck.
--
Unlimited in my Limits.
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Contributor
Contributor
6,722 Views
Registered: ‎09-15-2008

After digging around, I found the net name post-synthesis.What I wound up doing was building the project with no UCF file and then opening the NGD in the constraints editor. Some of my signals got named really weird things, presumably because earlier signals in other unreleated modules share the same names.

 

Is there any kind of a synthesis constraint I can attatch to the Verilog using the (*-CONSTRAINT-*) style of tagging that will make it earier for me to track the net and/or add timing constraints later? It's really lame that I'll have to do this every time the net names change due to module re-ordering.

 

 

 

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Explorer
Explorer
4,515 Views
Registered: ‎09-16-2010

This is a major pain when doing Xilinx based designs. A clock name shouldn't change depending on where it is routed. At the least, you should be able to constrain a clock based on its source path. For example, if I route a clock to a Chipscope module and the clock is still being used as it was previously except for this module, I shouldn't have to modify my constraints file. This is a huge time waster. It also means I have to babysit the build and make sure Translate didn't fail because the clock names were changed for whatever reason. 

Andrew
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