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Registered: ‎12-22-2008

How to fix the bug about uncorrected ODT,CSn width of MPMC

My software version is 14.6. I use Virtex 5(xc5vsx50t) to control DDR2 SDRAM(MT47H32M16). I have successfully generate the controller using MIG(from CORE Generator of ISE Design Tools). The controller can successfully run even under the highest clock frequency, that is 266MHz.


After validating the correctness of the hardware, I generate the DDR2 controller using MPMC under EDK. Since I want to choose the using banks, I use the integrated MIG GUI Flow. However, the pin assignment is different from the former one. And I find the reason is that there are more address/controller signals than before. After generating the core, I find several unexpected signals:


ddr2 odt[1], ddr2_ck[1], ddr2_ck_n[1], ddr2_cs_n[1]


Those signals are unexpected when using MT47H32M16 since its "ODT Width", "CSn width", "Clock Width" should be one. I am sure I have choose MT47H32M16 and set the "ODT Width", "CSn width", "Clock Width" to one under the "Memory Interface" tab of MPMC. The strange thing is that under the Ports of XPS, the width of those signals is one. And I find the "C_MEM_ODT_WIDTH","C_MEM_CE_WIDTH","C_MEM_CS_N_WIDTH"is 0 in mpmc.v.


Is this the bug of MPMC? And how to fix it? I appreciate it if you can give any idea.

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Registered: ‎12-22-2008

Re: How to fix the bug about uncorrected ODT,CSn width of MPMC

one additional remarks:


Since I find the "C_MEM_ODT_WIDTH""C_MEM_CS_N_WIDTH" is "1" in the mpmc_v2_1_0.mpd, so even

"C_MEM_ODT_WIDTH","C_MEM_CE_WIDTH","C_MEM_CS_N_WIDTH" is set to 0 in the mpmc.v, it is not important. However those signals shouldn't exist in the UCF.  How to fix it?

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