08-05-2009 08:01 AM
I am using AvNet's PCI Express board with Virtex-5. PCI Express deisgn is working ont he board and I can Read/Write to the BAR0 of the board using PCITree. But I am puzzled about how to read/write BAR0 in the MicroBlaze code? What offset I need to give in to XPcie_mReadReg to be able to read 1024 entries of BAR0?
08-06-2009 03:01 AM
I have seen one Avnet design for PCI Express it does not use XPS or Microblaze. PCI Tree is a PC program not requiring a FPGA Processor. To write a C program
running on the PC is a advanced skill because you have to know how to write a Windows Driver to talk to the PCI express interface. It can be done on the PC
much more easily if you use Jungo's Tool. They offer a trial of their product but is only for about 30 to 60 days. I think it costs alot to buy though something like 5 K.
08-06-2009 03:35 AM
Thanks for reply.
Actually I am talking about accessing BAR memory area from inside the FPGA. I am using PCI Express Endpoint Wrapper which connects with the PCI Express Endpoint. But I cant figure out how to read the values which I have written in the BAR memory area using PCITree. I have worked on Device drivers for Windows in the past so the Host side part is easier. Main problem is inside the FPGA where information is scant.
08-06-2009 08:58 AM - edited 08-06-2009 08:59 AM
I worked a little with XAPP859 (DMA). It requires serial communications/serial commands/data transfers to and from the PCIe device (no Microblaze)
done by state machines/memorys.
There is a new App note on the PCIe bridge that uses the Microblaze. Don't know a lot about how that would work.