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Registered: ‎04-02-2010

How to resolve or avoid PLB time out problem?

Hi everyone, I'm using EDK10.1 to simulate my Custom IP


I've got problems access PLB Bus


I wrote my own wrapper user_logic  to access PLB in Burst Read & Burst Write Mode(file is in attachment)


When I add my IP in the EDK and tried to use C code to test it(C code is in attachment too)


I found out that the wrapper works well on SRAM(both read & write are okay)


but when I tried to access DDR on my board, the timeout & Error signal asserted


I tried to find some documents to help me resolve it, but all I got is that the timeout happens when there's no response from slave after 16 cycles of request signal assert


I've checked the address of DDR(0x300000) & turn off the optimization of C compiler, but it still happens


how can I resolve this timeout problem?


really thanks for all the help, it has bothered me for whole week


thanks again for all your advice & help! : )

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Registered: ‎01-04-2008

Is the DDR accessible to the PLB core?  Is the PLB master port connected to a bus that is connected to the MPMC?

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