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Anonymous
Not applicable
8,421 Views

How to send/recieve data from multiple FSL?

Hello !! I have added 5 co-prossessor (multiplier) through FSL in Microblaze. how to send data to them? i use

putfsl(data(1), 0);

putfsl(data(2), 1);

putfsl(data(3) 2);

putfsl(data(4),3);

putfsl(data(5),4);

and to recieve..

getfsl (out(1), 0);

getfsl (out(2), 1);

getfsl (out(3), 2);

getfsl (out(4), 3);

getfsl (out(5), 4);

 

but it didnt show the output.....pls help me

Amit 

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Xilinx Employee
Xilinx Employee
8,420 Views
Registered: ‎08-06-2007

Hi,

 

Hard to tell you exactly what can be wrong with so little information.

 

- Have you configured MicroBlaze with 5 FSL interfaces?

- Have you connected the co-processors to MicroBlaze correctly?

- Have you made sure that clock and reset are connected to the FSL busses?

- Since you are using blocking FSL put and get, are you sure that your co-processors actually returns a value? MicroBlaze will hang if not so

- Have you simulated this system?

- Have you tried with only one co-processor?

 

Göran

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Anonymous
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thanks a lot for ur post. here is ur answer...

 

Have you configured MicroBlaze with 5 FSL interfaces?  ---> first i create new perifaral using create/import wizard.then import it via same wizards.

- Have you connected the co-processors to MicroBlaze correctly? ---->then i add it 5 times through configure_coprocessor option

- Have you made sure that clock and reset are connected to the FSL busses?----> yes clk & rst is shown in port diagram

- Since you are using blocking FSL put and get, are you sure that your co-processors actually returns a value? MicroBlaze will hang if not so

- Have you simulated this system? ----> yes it returns...one fsl link is working perfectly...but when i add other pufsl ot getfsl it hangs....

- Have you tried with only one co-processor?

 

 thanx in advance...

amit 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2007

Hi,

 

Can you show the .mhs file?

 

Göran

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Anonymous
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 thank you !! here is my .mhs file...

 

 

 

 

 

 

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1 Build EDK_K.15
# Wed Apr 15 11:11:41 2009
# Target Board:  Xilinx Spartan-3E Starter Board Rev D
# Family:    spartan3e
# Device:    XC3S500e
# Package:   FG320
# Speed Grade:  -4
# Processor: microblaze_0
# System clock frequency: 50.00 MHz
# On Chip Memory :  16 KB
# Total Off Chip Memory :  64 MB
# - DDR_SDRAM =  64 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I
 PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O, DIR = IO
 PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [15:0]
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER HW_VER = 7.10.a
 PARAMETER C_AREA_OPTIMIZED = 1
 PARAMETER C_FSL_LINKS = 5
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE SFSL0 = fsl1_0_to_microblaze_0
 BUS_INTERFACE MFSL0 = microblaze_0_to_fsl1_0
 BUS_INTERFACE SFSL2 = fsl1_2_to_microblaze_0
 BUS_INTERFACE MFSL2 = microblaze_0_to_fsl1_2
 BUS_INTERFACE SFSL3 = fsl1_3_to_microblaze_0
 BUS_INTERFACE MFSL3 = microblaze_0_to_fsl1_3
 BUS_INTERFACE SFSL4 = fsl1_4_to_microblaze_0
 BUS_INTERFACE MFSL4 = microblaze_0_to_fsl1_4
 BUS_INTERFACE SFSL1 = fsl1_1_to_microblaze_0
 BUS_INTERFACE MFSL1 = microblaze_0_to_fsl1_1
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.02.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_DCE
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_DCE_RX
 PORT TX = fpga_0_RS232_DCE_TX
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR_SDRAM
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_NUM_PORTS = 1
 PARAMETER C_MEM_PARTNO = MT46V32M16-6
 PARAMETER C_SPECIAL_BOARD = S3E_STKIT
 PARAMETER C_MEM_BANKADDR_WIDTH = 2
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_MEM_DQS_WIDTH = 2
 PARAMETER C_MEM_DM_WIDTH = 2
 PARAMETER C_MEM_TYPE = DDR
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
 PARAMETER C_MPMC_BASEADDR = 0x8c000000
 PARAMETER C_MPMC_HIGHADDR = 0x8fffffff
 PARAMETER C_SPLB0_NATIVE_DWIDTH = 32
 BUS_INTERFACE SPLB0 = mb_plb
 PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
 PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
 PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
 PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
 PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
 PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
 PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
 PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
 PORT MPMC_Clk0 = DDR_SDRAM_mpmc_clk_s
 PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
 PORT MPMC_Rst = sys_periph_reset
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = mb_plb
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 50000000
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT1_FREQ = 100000000
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = DCM0
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT2_PHASE = 90
 PARAMETER C_CLKOUT2_GROUP = DCM0
 PORT CLKOUT0 = sys_clk_s
 PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s
 PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl1_0_to_microblaze_0
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl1
 PARAMETER INSTANCE = fsl1_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE MFSL = fsl1_0_to_microblaze_0
 BUS_INTERFACE SFSL = microblaze_0_to_fsl1_0
 PORT FSL_Clk = sys_clk_s
END

BEGIN fsl_v20
 PARAMETER INSTANCE = microblaze_0_to_fsl1_0
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl1_2_to_microblaze_0
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl1
 PARAMETER INSTANCE = fsl1_2
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE MFSL = fsl1_2_to_microblaze_0
 BUS_INTERFACE SFSL = microblaze_0_to_fsl1_2
 PORT FSL_Clk = sys_clk_s
END

BEGIN fsl_v20
 PARAMETER INSTANCE = microblaze_0_to_fsl1_2
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl1_3_to_microblaze_0
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl1
 PARAMETER INSTANCE = fsl1_3
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE MFSL = fsl1_3_to_microblaze_0
 BUS_INTERFACE SFSL = microblaze_0_to_fsl1_3
 PORT FSL_Clk = sys_clk_s
END

BEGIN fsl_v20
 PARAMETER INSTANCE = microblaze_0_to_fsl1_3
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl1_4_to_microblaze_0
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl1
 PARAMETER INSTANCE = fsl1_4
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE MFSL = fsl1_4_to_microblaze_0
 BUS_INTERFACE SFSL = microblaze_0_to_fsl1_4
 PORT FSL_Clk = sys_clk_s
END

BEGIN fsl_v20
 PARAMETER INSTANCE = microblaze_0_to_fsl1_4
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl1_1_to_microblaze_0
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl1
 PARAMETER INSTANCE = fsl1_1
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE MFSL = fsl1_1_to_microblaze_0
 BUS_INTERFACE SFSL = microblaze_0_to_fsl1_1
 PORT FSL_Clk = sys_clk_s
END

BEGIN fsl_v20
 PARAMETER INSTANCE = microblaze_0_to_fsl1_1
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END


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Xilinx Employee
Xilinx Employee
8,367 Views
Registered: ‎08-06-2007

Hi,

 

Your .mhs look ok, so the problem is either in the software or in your co-processors.

 

I would short-circuit the FSL connections so MicroBlaze is sending data to itself.

Just connect the FSL masters through a FSL bus to the corresponding FSL slaves.

 

If you now run your application and you can read the data you have sent than your application is fine and the problem is in your coprocessors.

If it doesn't work than there is something in your application that causes your problem.

 

How many words does your FSL coprocessors want before sending back any result?

 

Göran

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Anonymous
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8,365 Views

hello Goren !!

thank you very much. you were right , there is problem in my c application. the code is running perfectly when i remove my XPS_TIMER. what may be the reason? i am sending my C Code..pls note it....

 

#include "xparameters.h"
#include "mb_interface.h"
#include "xbasic_types.h"
#include "fsl.h"
#include "xutil.h"
int main(void)
{
  int data_to_local_link[10] ={134,112,17,18,19,10,11,12,23,87};
 
 
int count,XPS_Timer;
int i;
int k =0;
int r=0;
 
 
int data_back_local_link[7];
   
//XTmrCtr_Initialize(& XPS_Timer, XPAR_XPS_TIMER_1_DEVICE_ID);
//XTmrCtr_SetResetValue(& XPS_Timer, 0, 0x00000000);
//XTmrCtr_Reset(& XPS_Timer, 0);
 
 
print("        #########################################\n\r");
print("\n\r");
print("\n\r");
         


        print("Write input values to the Local Link bus\n\r");


//XTmrCtr_Start(& XPS_Timer, 0);

 
    putfsl(data_to_local_link[0],0);
   putfsl(data_to_local_link[1],0);
    putfsl(data_to_local_link[2],1);
   putfsl(data_to_local_link[3],1);
    putfsl(data_to_local_link[4],2);     
    putfsl(data_to_local_link[5],2);
   putfsl(data_to_local_link[6],3);
    putfsl(data_to_local_link[7],3);
   putfsl(data_to_local_link[8],4);
    putfsl(data_to_local_link[9],4);
   
   
       
        for(i=0;i<10;i++){
       xil_printf("   %d; ",data_to_local_link[k]);
       
        k++;
        }
         
    print("\n\r");
    print("\n\r");
         
         




getfsl( data_back_local_link[0],0);
getfsl( data_back_local_link[1],1);
getfsl( data_back_local_link[2],2);
getfsl( data_back_local_link[3],3);
getfsl( data_back_local_link[4],4);





    //r++;
   
    //}
   
       
//XTmrCtr_Stop(& XPS_Timer, 0);
//count = XTmrCtr_GetValue(& XPS_Timer, 0);
//xil_printf(" total No. of clock required is...%d\r\n",count);
    
    for(i=0;i<5;i++){
    xil_printf(" recived data is.. %d; \n\r",data_back_local_link[i]); }
   
   
    
         
     
    print("-------------------------------------------------------------\n\r");
    print("\n\r");
//};
 
 
 
while(1);
 
return 1;
 

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Xilinx Employee
Xilinx Employee
8,356 Views
Registered: ‎08-06-2007

Hi,

 

Does your application fit in the memory?

Do you have enough stack and heap memory allocated?

 

When you have the timer code in your application what is the last print statement printed in the terminal?

 

Göran

 

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Anonymous
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8,352 Views

Sir,

 I have 16 Kbyte BRAM available...last ststement on terminal is ....

 

"fata to local link.....134,112,17,18,19,10,11,12,23,87 "  ------>  that is just after i start timer and give putfsl command...the code below that is not showing..(it hangs..)

 

 

thank you for ur guidence!!

amit 

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Anonymous
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HI !!

how to know wether my application is fit in the memory or not? 

how to know the status of stack and heap memory allocated?

 

pls reply.

amit 

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Xilinx Employee
Xilinx Employee
7,267 Views
Registered: ‎08-06-2007

Hi,

 

You didn't reply on the size of the stack and heap.

Try to make them much larger and see if it change the behaviour.

 

Göran

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Anonymous
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7,265 Views

     How to get  the size of the stack and heap ?

if i run only one FSL thantimer wors.. so pls help me to increse the size of memory...

amit 

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Xilinx Employee
Xilinx Employee
7,255 Views
Registered: ‎08-06-2007

Hi,

 

In XPS for software projects you can choose your application and right-click on it.

This will popup a menu and select "Compiler Options".

In the first tab (at the bottom) you can select "Stack Size" and "Heap Size".

I would pick at least 4 kbyte for the stack. The heap can be pretty small since you don't do much that requires a larger heap.

 

Göran

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Anonymous
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hi ! i have extend my stack upto 4k and heap size as follows .pls see the following  linker id..   still not getting results  :( ! it hangs...

 

 

 

/*******************************************************************/
/*                                                                 */
/* This file is automatically generated by linker script generator.*/
/*                                                                 */
/* Version: Xilinx EDK 10.1 EDK_K.15                                */
/*                                                                 */
/* Copyright (c) 2004 Xilinx, Inc.  All rights reserved.           */
/*                                                                 */
/* Description : MicroBlaze Linker Script                          */
/*                                                                 */
/*******************************************************************/

_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x4000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000;

/* Define Memories in the system */

MEMORY
{
   ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000050, LENGTH = 0x00007FB0
   DDR_SDRAM_C_MPMC_BASEADDR : ORIGIN = 0x8C000000, LENGTH = 0x04000000
}

/* Specify the default entry point to the program */

ENTRY(_start)

/* Define the sections, and where they are mapped in memory */

SECTIONS
{
.vectors.reset 0x00000000 : {
   *(.vectors.reset)
}

.vectors.sw_exception 0x00000008 : {
   *(.vectors.sw_exception)
}

.vectors.interrupt 0x00000010 : {
   *(.vectors.interrupt)
}

.vectors.hw_exception 0x00000020 : {
   *(.vectors.hw_exception)
}

.text : {
   *(.text)
   *(.text.*)
   *(.gnu.linkonce.t.*)
} > ilmb_cntlr_dlmb_cntlr

.init : {
   KEEP (*(.init))
} > ilmb_cntlr_dlmb_cntlr

.fini : {
   KEEP (*(.fini))
} > ilmb_cntlr_dlmb_cntlr

.rodata : {
   __rodata_start = .;
   *(.rodata)
   *(.rodata.*)
   *(.gnu.linkonce.r.*)
   __rodata_end = .;
} > ilmb_cntlr_dlmb_cntlr

.sdata2 : {
   . = ALIGN(8);
   __sdata2_start = .;
   *(.sdata2)
   *(.sdata2.*)
   *(.gnu.linkonce.s2.*)
   . = ALIGN(8);
   __sdata2_end = .;
} > ilmb_cntlr_dlmb_cntlr

.sbss2 : {
   __sbss2_start = .;
   *(.sbss2)
   *(.sbss2.*)
   *(.gnu.linkonce.sb2.*)
   __sbss2_end = .;
} > ilmb_cntlr_dlmb_cntlr

.data : {
   . = ALIGN(4);
   __data_start = .;
   *(.data)
   *(.data.*)
   *(.gnu.linkonce.d.*)
   __data_end = .;
} > ilmb_cntlr_dlmb_cntlr

.got : {
   *(.got)
} > ilmb_cntlr_dlmb_cntlr

.got1 : {
   *(.got1)
} > ilmb_cntlr_dlmb_cntlr

.got2 : {
   *(.got2)
} > ilmb_cntlr_dlmb_cntlr

.ctors : {
   __CTOR_LIST__ = .;
   ___CTORS_LIST___ = .;
   KEEP (*crtbegin.o(.ctors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
   KEEP (*(SORT(.ctors.*)))
   KEEP (*(.ctors))
   __CTOR_END__ = .;
   ___CTORS_END___ = .;
} > ilmb_cntlr_dlmb_cntlr

.dtors : {
   __DTOR_LIST__ = .;
   ___DTORS_LIST___ = .;
   KEEP (*crtbegin.o(.dtors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
   KEEP (*(SORT(.dtors.*)))
   KEEP (*(.dtors))
   __DTOR_END__ = .;
   ___DTORS_END___ = .;
} > ilmb_cntlr_dlmb_cntlr

.eh_frame : {
   *(.eh_frame)
} > ilmb_cntlr_dlmb_cntlr

.jcr : {
   *(.jcr)
} > ilmb_cntlr_dlmb_cntlr

.gcc_except_table : {
   *(.gcc_except_table)
} > ilmb_cntlr_dlmb_cntlr

.sdata : {
   . = ALIGN(8);
   __sdata_start = .;
   *(.sdata)
   *(.sdata.*)
   *(.gnu.linkonce.s.*)
   __sdata_end = .;
} > ilmb_cntlr_dlmb_cntlr

.sbss : {
   . = ALIGN(4);
   __sbss_start = .;
   *(.sbss)
   *(.sbss.*)
   *(.gnu.linkonce.sb.*)
   . = ALIGN(8);
   __sbss_end = .;
} > ilmb_cntlr_dlmb_cntlr

.tdata : {
   __tdata_start = .;
   *(.tdata)
   *(.tdata.*)
   *(.gnu.linkonce.td.*)
   __tdata_end = .;
} > ilmb_cntlr_dlmb_cntlr

.tbss : {
   __tbss_start = .;
   *(.tbss)
   *(.tbss.*)
   *(.gnu.linkonce.tb.*)
   __tbss_end = .;
} > ilmb_cntlr_dlmb_cntlr

.bss : {
   . = ALIGN(4);
   __bss_start = .;
   *(.bss)
   *(.bss.*)
   *(.gnu.linkonce.b.*)
   *(COMMON)
   . = ALIGN(4);
   __bss_end = .;
} > ilmb_cntlr_dlmb_cntlr

.newsection : {
   __newsection_start = .;
   *(.newsection)
   __newsection_end = .;
} > ilmb_cntlr_dlmb_cntlr

.newsection : {
   __newsection_start = .;
   *(.newsection)
   __newsection_end = .;
} > ilmb_cntlr_dlmb_cntlr

_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );

_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );

/* Generate Stack and Heap definitions */

.heap : {
   . = ALIGN(8);
   _heap = .;
   _heap_start = .;
   . += _HEAP_SIZE;
   _heap_end = .;
} > ilmb_cntlr_dlmb_cntlr

.stack : {
   _stack_end = .;
   . += _STACK_SIZE;
   . = ALIGN(8);
   _stack = .;
   __stack = _stack;
} > ilmb_cntlr_dlmb_cntlr

}

 

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Xilinx Employee
Xilinx Employee
7,244 Views
Registered: ‎08-06-2007

Hi,

 

Could you email me the .elf file?

I can take a look at it to see if I found anything strange.

 

Göran

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Anonymous
Not applicable
7,229 Views

hello gouran!

please find the ateechjment containing my .ucf . I am apollogise if any of my silliy post makes you bored.But this project is having so much importance for me ....

amit 

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Anonymous
Not applicable
7,198 Views

hello goran!!

 i have tried to extend my stack size in
order to run my application with XPS_TIMER.but it doesnt shows anything
on terminal..if i run my application without timer than it
works..please send me the sollution..

thanking you..

amit

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Xilinx Employee
Xilinx Employee
7,196 Views
Registered: ‎08-06-2007

Hi,

 

Been busy with my work.

I can't find anything weird in your program.

Have you tried to simulate your system or debug it with XMD/SDK?

 

Göran

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Anonymous
Not applicable
7,194 Views

hi not yet ...i will try it now.. thanks!!

amit 

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