How to triplicate program across BRAMs?

[dev2293]

Hi,

I am trying to load the program post compilation into the 3 BRAM memories for Instruction Bus. Following is my block design.

The scrubber IP scrubs the BRAMs through PORTBs and PORTA is for the data flow from the Microblaze.with a TMR voting mechanism.

When I don't use the scrubber IP on the Instruction Bus the program works, even the scrubber on Data Bus works.

I have tried to work with the MMI files, but they don't seem to have any configurations for the Instruction Bus. And, I the Updatemem requires a mmi file to produce a mem file from an ELF file.

Is there a way in Vivado or Vitis 2019.2 to make sure the program gets loaded to the 3 BRAM memories equally, so that the voter does not majority vote out the actual data?

[stephenm]

Vivado will create an MMI file for all memory mapped BRAMs. This MMI file is then added to your XSA file and used in Vitis (updatemem specifically).

However, I doubt the MMI file is getting created as you have a scrubber IP added between the bram controller and the BRAM?

If htis is the case, then you would need to manually create the MMI file. The wiki below describes how to do this:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842458/Understanding+MEMDATA+flow+and+how+to+manually+create+MMI+file

[dev2293]

Hi,

I followed the instructions on "https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842458/Understanding+MEMDATA+flow+and+how+to+manually+create+MMI+file"

Created the MMI files and ran the updatemem utility 3 times to populate the bit files with the ELF data.

However, it did not work. I saw a lot of garbage data being sent through the USB-Serial in the terminal through Vitis, i thought maybe the Uart Drivers were working, but its does the same in both the situations where the data was written to just 2 BRAM and 3 BRAM so i am guessing the program was not even functional when downloaded into the FPGA.

The Updatemem was successful in compilation, but seems like something is wrong.

Would you be able to suggest what went wrong?

[dev2293]

Hi,

I solved my issue of repeatedly creating mmi file by using an XPM memory. 

However, I am not faced with the issue of loading the program into memory. 

I have my program in ELF format, and i do not have access to data2mem since I am using Vivado 2020.1 

Updatemem requires a MEM file to load data into the BRAMs generated via XPM. 

So it boils down to, how to generate a MEM file for a program? or how to force updatemem to use an ELF file and program the XPM memories?

-Thanks

[stephenm]

I am not sure if XPM is supported in updatemem. Updatemem only support RAMB36, and doesnt support bitlane mismatch in the MMI

That said, there is a writememinfo option in updatemem that will generate a MEM file

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug898-vivado-embedded-design.pdf