10-20-2011 11:45 AM
I wonder if anybody can direct me to a simple way to instantiate and LOCate the IDELAYCTRL primitives in EDK. Here is my specific situation.
Using EDK 12.4, and a V6LX130T-based custom board (which is being designed) I am trying to insure the pinout will work. In XPS I have both the LLTEMAC hard Temac core and an MPMC DDR3 RAM core instantiated, each of which requires (at least one) IDELAYCTRL element. I have struggled through using PlanAhead to LOC the IDELAYCTRLs "by hand", and have gotten all the way through PAR. But then when I change the pinout a little, MAP fails (after 4 hours) in Phase 10.8, with errors related to the LOCing of the IDELAYCTRLs.
It seems like such a simple bit of work (compared to everything else the toolflow does): if you need an IDELAYCTRL in a given clock region, instantiate one, and if you don't, don't.
I read on one of the forums that the right way to do it is to instantiate exactly one IDELAYCTRL in the design, without LOC constraint, and the tools should then replicate it as needed. I tried this (byt setting the LLTEMAC NUMIDELAYCTRL =0, and the MPMC NUMIDELAYCTRL=1), but then it seemed to be missing the one for the LLTEMAC (which is after all what I told it to do).
Help greatly appreciated.
10-20-2011 12:57 PM
The method that instantiates exactly one IDELAYCTRL and doesn't LOC it can only work if
you don't need independent control or status signals.
I haven't worked with V6, but at least for V5, the IDELAYCTRL elements correspond to exactly
one IO bank each. Changing pinout will only affect the IDELAYCTRL if you move the pins
for a particular controller into a different bank.
If you haven't locked down the pinout of a design, then as you found out, the process of
hand LOCing the IDELAYCTRLs becomes an iterative process. So you really want to use
the single unLOCed IDELAYCTRL if possible. The problem comes when you have multiple
modules that are not fully under your own control (read EDK) and each one needs to have
the "ready" output routed to it. When you assign 0 IDELAYCTRL elements, it's not clear how
EDK handles this.
10-23-2011 07:27 AM
In general, you would instantiate one IDELAYCTRL per IP core and then use the IODELAY_GROUP constraint to group all IDELAYCTRL, IODELAY within the same core. If you use this approach, do NOT LOC the IDELAYCTRL because the tool will replicate the IDELAYCTRL and place them where needed. Please check the Constraint UG for more details on the IODELAY_GROUP constraint. (By the way, download Xilinx Document Navigator to manage all Xilinx documents).
If you want to manually instantiate IDELAYCTRL's by hand and LOC them down by hand, ADEPT may come handy where IDELAYCTRLs need to be placed.